ISL29020_14 Datasheet, PDF (6/11 Pages) Intersil Corporation – A Low Power, High Sensitivity, Light-to Digital Sensor With I2C Interface

ISL29020
.
TABLE 7. RESOLUTION/WIDTH
BITS 3:2
0:0
0:1
1:0
1:1
NUMBER OF CLOCK CYCLES
2¹⁶ = 65,536
2¹² = 4,096
2⁸ = 256
2⁴ = 16
5. Range: Bits 1 and 0. The Full Scale Range (FSR) can be
adjusted via I²C using Bits 1 and 0. Table 8 lists the
possible values of FSR for the 500kΩ R_EXT resistor.
TABLE 8. RANGE/FSR LUX
BITS
1:0 k RANGE(k)
FSR (LUX) @ FSR (LUX) @ IR
ALS SENSING
SENSING
0:0 1 Range1
1,000
Refer to page 2
0:1 2 Range2
4,000
Refer to page 2
1:0 3 Range3
16,000
Refer to page 2
1:1 4 Range4
64,000
Refer to page 2
Data Registers (01 hex and 02 hex)
The device has two 8-bit read-only registers to hold a 16-bit
data from ADC or Timer. The most significant byte is
accessed at 02 hex, and the least significant byte is
accessed at 01 hex. The registers are refreshed after every
conversion cycle.
TABLE 9. DATA REGISTERS
ADDRESS
(hex)
CONTENTS
01 Least-significant byte of most recent ADC or Timer data.
02 Most-significant byte of most recent ADC or Timer data.
Calculating Lux
The ISL29020’s ADC output codes, DATA, are directly
proportional to lux in the ambient light sensing, as shown in
Equation 1.
E_cal = α × DATA
(EQ. 1)
Here, E_cal is the calculated lux reading. The constant α is
determined by the Full Scale Range and the ADC’s
maximum output counts. The constant can also be viewed
as the sensitivity: the smallest lux measurement the device
can measure, as shown in Equation 2.
α
=
-^R-----^a----ⁿ---^g----^e----⁽--^k----⁾-
Count_max
(EQ. 2)
Here, Range(k) is defined in Table 8. Count_max is the
maximum output counts from the ADC.
The transfer function used for each timing mode becomes:
INTERNAL TIMING MODE
E
=
R_-----a_----n_----g_----e_----(_--k_----)
2ⁿ
×
D
A
T
A
(EQ. 3)
Here, n = 4, 8, 12 or 16. This is the number of ADC bits
programmed in the command register. 2ⁿ represents the
maximum number of counts possible from the ADC output in
Internal-Timing mode. Data is the ADC output stored in the
data registers (01 hex and 02 hex).
EXTERNAL TIMING MODE
E
=
R_-----a_----n_----g_----e_----(_--k_----)
Timer
× DATA
(EQ. 4)
Here, Timer sets up the ADC’s maximum count reading and
it is the number of clock cycles accrued in the integration
time (set by sync_I²C pulses) in External-Timing mode. It is
stored in the data registers 01h and 02h when the command
is coded as 1xx101xx. Data is the ADC output. In this mode,
the command has to be sent out again with code 1xx100xx
to request the ADC output data from registers 01h and 02h.
External Scaling Resistor R_EXT for f_OSC and
Range
The ISL29020 uses an external resistor R_EXT to fix its
internal oscillator frequency, f_OSC and the light sensing
range, Range. f_OSC and Range are inversely proportional to
R_EXT. For user simplicity, the proportionality constant is
referenced to 500kΩ:
Range
=
-⁵---⁰---⁰----^k---^Ω---
R_EXT
×
R
a
n
ge
(
k
)
(EQ. 5)
f_OSC
=
5_----0_---0_----k_---Ω_---
R_EXT
×
725
k
H
z
(EQ. 6)
Integration Time or Conversion Time
Integration time is the period during which the device’s
analog-to-digital ADC converter samples the photodiode
current signal for a measurement. Integration time, in other
words, is the time to complete the conversion of analog
photodiode current into a digital signal (number of counts).
Integration time affects the measurement resolution. For
better resolution, use a longer integration time. For short and
fast conversions, use a shorter integration time.
The ISL29020 offers user flexibility in the integration time to
balance resolution, speed and noise rejection. Integration time
can be set internally or externally by programming the bit 4 of
the command register 00(hex).
INTEGRATION TIME IN INTERNAL-TIMING MODE
Most applications will use the Internal-Timing mode. In this
mode, f_OSC and ADC n-bits resolution determine the
integration time, t_int, as shown in Equation 7.
t_int
=
2ⁿ
×
------¹-------
f_OSC
=
2ⁿ × ₇----₂---₅----_k---_H--^R---_z--^E---_×-^X---^T-₅---₀---₀----_k----_Ω--
(EQ. 7)
where n is the number of bits of resolution and n = 4, 8, 12 or
16. 2ⁿ, therefore, is the number of clock cycles. n can be
programmed at the command register 00(hex) bits 3 and 2.
6
FN6505.1
August 20, 2009