ISL29020_14 Datasheet, PDF(5/11 Page) Intersil Corporation – A Low Power, High Sensitivity, Light-to Digital Sensor With I2C Interface

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ISL29020_14 Datasheet, PDF (5/11 Pages) Intersil Corporation – A Low Power, High Sensitivity, Light-to Digital Sensor With I2C Interface

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ISL29020

Register Set

There are three 8-bit registers in the ISL29020. Table 1 summarizes their functions.

TABLE 1. REGISTER SET

BIT

ADDR REG NAME

7

6

5

4

3

2

00h COMMAND

EN

MODE

LIGHT

RES2

RES1

RES0

01h

DATALSB

D7

D6

D5

D4

02h

DATAMSB

D15

D14

D13

D12

D3

D2

D11

D10

1

RANGE1

D1

D9

0

RANGE0

D0

D8

DEFAULT

00h

00h

00h

TABLE 2. WRITE ONLY REGISTERS

ADDRESS

NAME

FUNCTIONS/DESCRIPTION

b1xxx_xxxx sync_I2C Writing a logic 1 to this address bit

ends the current ADC-integration

and starts another. Used only with

External Timing Mode.

Command Register (00 hex)

The Read/Write command register has five functions:

1. Enable: Bit 7. This bit enables the ISL29020 with logic 1

and powers down ISL29020 with logic 0.

TABLE 3. ENABLE

BIT 7

OPERATION

0

Power-down the device

1

Enable the device

2. Measurement Mode: Bit 6. This bit controls the two

measurement modes of the device. A logic 0 puts the

device in the one-time measurement mode in which the

device is automatically shut-down after each

measurement. A logic 1 puts the device in the continuous

measurement mode in which data is collected

continuously.

TABLE 4. MEASUREMENT MODE

BIT 6

OPERATION

0

One-time measurement

1

Continuous measurement

3. Light Sensing: Bit 5. This bit programs the device to do the

ambient light or the infrared (IR) light sensing. A logic 0,

requests for the ambient light sensing and a logic 1

requests for the IR sensing.

TABLE 5. LIGHT SENSING

BIT 5

OPERATION

0

Ambient light sensing

1

Infrared light sensing

4. Timing Mode and Resolution: Bits 4, 3 and 2. These three

bits determine whether the integration time is done

internally or externally, and the number of bits for ADC. In

Internal Timing Mode, integration time is determined by

an internal oscillator (fOSC) and the n-bit (n = 4, 8, 12, 16)

counter inside the ADC. In External Timing Mode, the

integration time is determined by the time between two

consecutive sync_I2C pulse commands.

TABLE 6. TIMING MODE AND RESOLUTION

BITS 4:3:2

MODE

0:0:0 Internal Timing, 16-bit ADC data output

0:0:1 Internal Timing, 12-bit ADC data output

0:1:0 Internal Timing, 8-bit ADC data output

0:1:1 Internal Timing, 4-bit ADC data output

1:0:0 External Timing, ADC data output

1:0:1 External Timing, Timer data output

1:1:0 Reserved

1:1:1 Reserved

With Bit 4 set to 0, the device is configured to run in the

Internal-Timing mode. For example, the command register

content should be 1xx000xx to request 16-bit ADC in the

internal-timing mode.

With Bit 4 set to 1, the device is configured to run in the

External-Timing mode. For the external timing, the command

1xx101xx needs to be sent to request the Timer data, the

number of clock cycles counted within the duration between

the two sync pulses (refer to Table 2). The Timer count is

read from register 01h (LSB) and 02h (MSB). The command

1xx100xx needs to be sent to request the ADC conversion.

The ADC data is also read from register 01h (LSB) and 02h

(MSB).

Bits 3 and 2 determine the number of clock cycles per

conversion in the Internal-Timing mode. Changing the

number of clock cycles does more than just change the

resolution of the device. It also changes the integration

time, which the ADC uses to sample the photodiode

current signal for a measurement.

5

FN6505.1

August 20, 2009

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