ISL24212 Datasheet, PDF (6/12 Pages) Intersil Corporation – Programmable VCOM Calibrator with EEPROM and Output Buffer

ISL24212
Application Information
LCD panels have a V_COM (common voltage) that must be precisely
set to minimize flicker. Figure 3 shows a typical V_COM adjustment
circuit using a mechanical potentiometer, and the equivalent
circuit replacement using the ISL24212. Having a digital counter
interface enables automatic, digital flicker minimization during
production test and alignment. After programming, the counter
interface is no longer needed - the ISL24212 automatically powers
up with the correct V_COM voltage programmed previously.
The ISL24212 uses a digitally controllable potentiometer (DCP),
with 256 steps of resolution (see Figure 4) to change the current
drawn at the DVR_OUT pin, which then changes the voltage
created by the R₁ - R₂ resistor divider (see Figure 5). The DVR_OUT
voltage is then buffered by A2 to generate a buffered output voltage
at the V_{COM_OUT} pin, capable of directly driving the V_COM input of
an LCD panel. The amount of current sunk is controlled by the
setting of the DCP, which is recalled at power-up from the
ISL24212’s internal EEPROM. The EEPROM is typically
programmed during panel manufacture. As noted in the
“Electrical Specifications” on page 4, the ISL24212 requires a
minimum AV_DD voltage of 10.8V for EEPROM programming, but
will work in normal operation down to 4.5V after the EEPROM
has been programmed, with no additional EEPROM writing.
AVDD
RA
RB
R1 = RA
R2 = RB+RC
RC
RSET = RARB + RARC
20RB
VCOM
AVDD
VDD
AVDD
R1
ISL24212
IOUT
VCOM_OUT
DVR_OUT
INN
R2
SET
RSET
VCOM
FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT
DCP (Digitally Controllable Potentiometer)
The DCP controls the voltage that ultimately controls the SET
current. Figure 4 shows the relationship between the register
value and the DCP’s tap position. Note that a register value of 0
selects the first step of the resistor string. The output voltage of
the DCP is given in Equation 1:
V_DCP
=
⎛
⎝
R_-----e_---g_----i_--s_---t_---e_-2--r_-5--V_--6-a_----l_--u_----e_----+-----1_{--⎠⎞}
⎛
⎝
A_----2-V_{---0D----D--⎠⎞}
(EQ. 1)
AV_DD
19R
AV_DD
20
REGISTER
VALUE
255
254
253
252
V_DCP
R
251
2
1
0
FIGURE 4. SIMPLIFIED SCHEMATIC OF DCP
Output Current Sink
Figure 5 shows the schematic of the DVR_OUT current sink. The
combination of amplifier A1, transistor Q1, and resistor R_SET
forms a voltage-controlled current source, with the voltage
determined by the DCP setting.
AVDD
AVDD
R1
DVR_ OUT
I _{DVR_OUT}
VDCP
A1
Q1
A2
VSAT
R2
VCOM_OUT
VOUT
INN
GND
SET
IOUT
VSET = VDCP = IOUT * RSET
RSET
FIGURE 5. CURRENT SINK CIRCUIT
The external R_SET resistor sets the full-scale (maximum) sink current
that can be pulled from the DVR_OUT node. The relationship
between I_{DVR_OUT} and Register Value is shown in Equation 2.
I_DVROUT
=
V_{----D----C---P--}
R_SET
=
⎛
⎝
R_-----e_---g_----i_--s_---t_---e_-2--r_-5--V_--6-a_----l_--u_----e_----+-----1_{--⎠⎞}
⎛
⎝
A_----2-V_{---0D----D--⎠⎞}
⎛
⎝
-_R----_S¹---_E---_T-_⎠⎞
(EQ. 2)
6
FN7590.0
March 15, 2011