ISL22346_14 Datasheet, PDF (6/16 Pages) Intersil Corporation – Low Noise, Low Power I2C™ Bus,128 Taps

ISL22346
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 21) (Note 5) (Note 21) UNIT
V_CCRamp V_CC Ramp Rate
t_D
Power-up Delay
0.2
VR_CegCisatbeor vreecValpl ocro,mtopDleCtePd,InaintidalI₂VCalIuneterface
in standby state
V/ms
3
ms
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
Cycles
EEPROM Retention
Temperature T < +55°C
50
Years
t_WC
Non-volatile Write Cycle Time
(Note 19)
12
20
ms
SERIAL INTERFACE SPECIFICATIONS
V_IL
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer LOW Voltage
-0.3
0.3*V_CC
V
V_IH
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer HIGH Voltage
0.7*V_CC
V_CC + 0.3
V
Hysteresis SDA and SCL Input Buffer Hysteresis
V_OL
SDA Output Buffer LOW Voltage,
Sinking 4mA
0.05*V_CC
0
V
0.4
V
Cpin A2, A1, A0, SHDN, SDA, and SCL Pin
(Note 20) Capacitance
10
pF
f_SCL
t_sp
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
400
kHz
50
ns
t_AA
t_BUF
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V_CC, until
Valid
SDA exits the 30% to 70% of V_CC window
Time the Bus Must be Free Before the SDA crossing 70% of V_CC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of V_CC
during the following START condition
1300
900
ns
ns
t_LOW Clock LOW Time
Measured at the 30% of V_CC crossing
1300
ns
t_HIGH Clock HIGH Time
Measured at the 70% of V_CC crossing
600
ns
t_SU:STA START Condition Setup Time
SCL rising edge to SDA falling edge; both
600
ns
crossing 70% of V_CC
t_HD:STA START Condition Hold Time
From SDA falling edge crossing 30% of V_CC
600
ns
to SCL falling edge crossing 70% of V_CC
t_SU:DAT Input Data Setup Time
From SDA exiting the 30% to 70% of V_CC
100
ns
window, to SCL rising edge crossing 30% of
V_CC
t_HD:DAT Input Data Hold Time
From SCL rising edge crossing 70% of V_CC
0
ns
to SDA entering the 30% to 70% of V_CC
window
t_SU:STO STOP Condition Setup Time
From SCL rising edge crossing 70% of V_CC,
600
ns
to SDA rising edge crossing 30% of V_CC
t_HD:STO STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;
1300
ns
or Volatile Only Write
both crossing 70% of V_CC
t_DH
Output Data Hold Time
From SCL falling edge crossing 30% of V_CC,
0
ns
until SDA enters the 30% to 70% of V_CC
window
t_R
SDA and SCL Rise Time
From 30% to 70% of V_CC
20 +
0.1*Cb
250
ns
6
FN6177.2
September 3, 2009