HI7191 Datasheet, PDF (6/24 Pages) Intersil Corporation – 24-Bit, High Precision, Sigma Delta A/D Converter

HI7191
Pin Descriptions
20 LEAD
DIP, SOIC PIN NAME
DESCRIPTION
1
SCLK Serial Interface Clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the
falling edge.
2
SDO Serial Data OUT. Serial data is read from this line when using a 3-wire serial protocol such as the
Motorola Serial Peripheral Interface.
3
SDIO Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial
Interface using a 2-wire serial protocol.
4
CS
Chip Select Input. Used to select the HI7191 for a serial data transfer cycle. This line can be tied to DGND.
5
DRDY An Active Low Interrupt indicating that a new data word is available for reading.
6
DGND Digital Supply Ground.
7
AV_SS Negative Analog Power Supply (-5V).
8
V_RLO External Reference Input. Should be negative referenced to V_RHI.
9
V_RHI External Reference Input. Should be positive referenced to V_RLO.
10
V_CM Common Mode Input. Should be set to halfway between AV_DD and AV_SS.
11
V_INLO Analog Input LO. Negative input of the PGIA.
12
V_INHI Analog Input HI. Positive input of the PGIA. The V_INHI input is connected to a current source that can be used to check
the condition of an external transducer. This current source is controlled via the Control Register.
13
AV_DD Positive Analog Power Supply (+5V).
14
AGND Analog Supply Ground.
15
DV_DD Positive Digital Supply (+5V).
16
OSC₂ Used to connect a crystal source between OSC₁ and OSC₂. Leave open otherwise.
17
OSC₁ Oscillator Clock Input for the device. A crystal connected between OSC₁ and OSC₂ will provide a clock to the
device, or an external oscillator can drive OSC₁. The oscillator frequency should be 10MHz (Typ).
18
RESET Active Low Reset Pin. Used to initialize the HI7191 registers, filter and state machines.
19
SYNC Active Low Sync Input. Used to control the synchronization of a number of HI7191s. A logic ‘0’ initializes the converter.
20
MODE Mode Pin. Used to select between Synchronous Self Clocking (Mode = 1) or Synchronous External Clocking
(Mode = 0) for the Serial Port.
Load Test Circuit
V₁
ESD Test Circuits
R₁
R₂
V±
C_ESD DUT
FIGURE 5A.
DUT
R₁
C_L (INCLUDES STRAY
CAPACITANCE)
FIGURE 4.
HUMAN BODY
C_ESD = 100pF
R₁ = 10MΩ
R₂ = 1.5kΩ
MACHINE MODEL
C_ESD = 200pF
R₁ = 10MΩ
R₂ = 0Ω
R₁
V ± ^R2
DUT
CHARGED DEVICE MODEL
R₁ = 1GΩ
R₂ = 1Ω
DIELECTRIC
FIGURE 5B.
1902