HI1386_03 Datasheet, PDF (6/7 Pages) Intersil Corporation – 8-Bit, 75 MSPS, Flash A/D Converter

HI1386
Electrical Specifications T_A = 25^oC, AV_EE = DV_EE = -5.2V, V_RT = 0V, V_RB = -2V (Note 1) (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Offset Voltage
E_OT
V_RT
E_OB
V_RB
DIGITAL INPUTS
8
18
32
mV
0
10
24
mV
Logic H Level, V_IH
Logic L Level, V_IL
Logic H Current, I_IH
Logic L Current, I_IL
Input Capacitance
-0.8V is Applied to Input
-1.6V is Applied to Input
-1.13
-
-
V
-
-
-1.50
V
0
-
50
µA
-50
-
50
µA
-
7
-
pF
DIGITAL OUTPUTS
Logic H Level, V_OH
Logic L Level, V_OL
TIMING CHARACTERISTICS
R_L = 620Ω to DV_EE
R_L = 620Ω to DV_EE
-1.03
-
-
V
-
-
-1.62
V
H Pulse Width of Clock, t_PW1
L Pulse Width of Clock, t_PW0
Output Rise Time, t_r
Output Fall Time, t_f
Output Delay, t_OD
POWER SUPPLY CHARACTERISTICS
R_L = 620Ω to DV_EE, 20% to 80%
R_L = 620Ω to DV_EE, 20% to 80%
6.6
-
-
ns
6.6
-
-
ns
-
0.9
-
ns
-
2.1
-
ns
4.0
6.5
9.0
ns
Supply Current, I_EE
-150
-104
-
mA
Power Consumption, P_D
Note 3
-
580
-
mW
NOTES:
1. Electrical Specifications guaranteed within stated operating conditions.
2. TPS: Times Per Sample.
3.
P_D
=
I_EE • V_EE +
(_---V_{----R----T----}-_---V_{----R----B----})_--²_-----
R_REF
4. T_A specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed.
Timing Diagram
ANALOG IN
CLK
CLK
t_DS
N
t_PW1
t_PW0
N+1
N+2
DIGITAL OUT
t_OD
N-1
80%
20%
N
80%
N+1
20%
t_r
t_f
FIGURE 1.
6