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HD-4702_06 Datasheet, PDF (6/8 Pages) Intersil Corporation – CMOS Programmable Bit Rate Generator
◁
HD-4702
Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HD-4702-9), TA = -55oC to +125oC (HD-4702-8)
SYMBOL
AC PARAMETER
LIMITS
MIN
MAX
UNITS
TEST
CONDITIONS
tPLH
Propagation Delay, IX to CO
-
350
ns
tPHL
-
275
ns
tPLH
Propagation Delay, CP to CO
-
260
ns
tPHL
-
220
ns
tPLH
Propagation Delay, CO to Qn
-
(Note 2)
ns
tPHL
-
(Note 2)
ns
tPLH
Propagation Delay, CO to Z
-
85
ns
tPHL
tTLH
tTHL
ts
Output Transition Time (Except OX)
Set-Up Time, Select to CO
-
75
ns
-
160
ns
-
75
ns
350
-
ns
VCC = 4.5V
CL ≤ 7pF on OX
CL = 50pF
(Note 1)
th
Hold Time, Select to CO
0
-
ns
ts
Set-Up Time, IM to CO
350
-
ns
th
Hold Time, IM to CO
0
-
ns
twCP(L)
Minimum Clock Pulse Width, Low (Notes 3, 4)
120
-
ns
twCP(H)
Minimum Clock Pulse Width, High (Notes 3, 4)
120
-
ns
twCP(L)
Minimum IX Pulse Width, Low (Note 4)
160
-
ns
twCP(H)
Minimum IX Pulse Width, High (Note 4)
160
-
ns
tPLH
Propagation Delay IX to CO
-
300
ns
tPHL
-
250
ns
tPLH
Propagation Delay CP to CO
-
215
ns
tPHL
tPLH
tPHL
tPLH
Propagation Delay CO to Qn
Propagation Delay CO to Z
-
195
ns
-
(Note 2)
ns
-
(Note 2)
ns
-
75
ns
VCC = 4.5V
CL ≤ 7pF on OX
CL = 15pF
(Note 1)
tPHL
-
65
ns
tTLH
Output Transition Time (Except OX)
-
80
ns
tTHL
-
40
ns
NOTES:
1. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (CL). Setup Times
(ts), Hold Times (th), and Minimum Pulse Widths (tw) do not vary with load capacitance.
2. For multichannel operation, Propagation Delay (CO to Qn) plus Set-Up Time, Select to CO, is guaranteed to be ≤ 367ns.
3. The first High Level Clock Pulse after ECP goes Low must be at least 350ns long to guarantee reset of all Counters.
4. It is recommended that input rise and fall times to the clock inputs (CP, IX) be less than 15ns.
6
FN2954.2
August 24, 2006
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