DG444DYZ-T Datasheet, PDF (6/12 Pages) Intersil Corporation – Monolithic, Quad SPST, CMOS Analog Switches

DG444, DG445
Test Circuits and Waveforms (Continued)
+15V
C V+
IMPEDANCE
ANALYZER
f = 1MHz
V_S
IN_X 0V, 2.4V
V_D
C
GND
V-
-15V
FIGURE 5. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT
Application Information
V_IN
GAIN₁
A_V = 1
GAIN₂
A_V = 10
GAIN₃
A_V = 20
GAIN₄
A_V = 100
FET INPUT
+15V
OP AMP
3
2
+_-
76
4
+5V
+15V
12
-15V ₁₃
2 ^VL
V+
3
1
15
14
16
10
11
9
7
6
8
DG444 OR DG445
V-
GND
4
5
-15V
V_OUT
R₁
90kΩ
R₂
5kΩ
R₃
4kΩ
R₄
1kΩ
GAIN ERROR IS DETERMINED ONLY BY
THE RESISTOR TOLERANCE, OP AMP OFFSET
AND CMRR WILL LIMIT ACCURACY OF CIRCUIT
V_{-----O----U----T--}
V_IN
=
-^R----¹----+-----^R-----²----+-----^R-----³----+-----^R-----⁴-
R₄
=
100
WITH SW₄ CLOSED
FIGURE 6. PRECISION WEIGHTED RESISTOR
PROGRAMMABLE GAIN AMPLIFIER
+5V
+15V
+15V
V_L
V+
1_{/4 DG444}
+5V
V_IN
0V
GND V-
+15V
V_OUT
0V
10kΩ
FIGURE 7. LEVEL SHIFTER
6
FN3586.10
June 4, 2007