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DG411DVZ-T Datasheet, PDF (6/13 Pages) Intersil Corporation – Monolithic Quad SPST, CMOS Analog Switches
◁
DG411, DG412, DG413
Electrical Specifications (Single Supply) Test Conditions: V+ = +12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4)
UNITS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 13.2V, V- = 0V
VIN = 0V or 5V
25
-
0.0001
1
μA
85
-
-
5
μA
Negative Supply Current, I-
25
-1
-0.0001
-
μA
85
-5
-
-
μA
Logic Supply Current, IL
25
-
0.0001
1
μA
85
-
-
5
μA
Ground Current, IGND
25
-1
-0.0001
-
μA
85
-5
-
-
μA
NOTES:
3. VIN = input voltage to perform proper function.
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Test Circuits and Waveforms
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing
edge of the output waveform.
3V
LOGIC
INPUT
0V
SWITCH
INPUT
VS
SWITCH
OUTPUT 0V
50%
tOFF
VO
90%
tr < 20ns
tf < 20ns
90%
SWITCH
INPUT
S1
IN1
LOGIC
INPUT
+5V
VL
+15V
V+
D1
SWITCH
OUTPUT
VO
GND
V-
-15V
RL
CL
tON
NOTE: Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENTS POINTS
Repeat test for all IN and S.
For load conditions, see Specifications. CL includes fixture and stray
capacitance.
VO
=
VS
---------------R-----L----------------
RL + rDS(ON)
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
3V
LOGIC
INPUT
0V
VS1
SWITCH
OUTPUT
(V01)
0V
VS2
90%
+5V
+15V
VL
V+
S1
D1
VS1 = 10V
S2
VS2 = 10V
IN1, IN2
D2
RL2
300Ω
VO2
RL1
300Ω
CL2
35pF
VO1
CL1
35pF
SWITCH
OUTPUT
VO2
0V
tD
90%
tD
LOGIC
INPUT
GND V-
-15V
CL includes fixture and
stray capacitance.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUITS
FIGURE 2. BREAK-BEFORE-MAKE TIME
6
FN3282.13
June 20, 2007
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