DG181 Datasheet, PDF (6/9 Pages) Intersil Corporation – High-Speed Drivers with JFET Switch

DG181 Series
DUAL SPST - DG181/182
TEST CONDITIONS
V_IN “ON” = 0.8V
All Channels
V_IN “OFF” = 2.0V
All Channels
NOTE:
1. Switch states are for logic “1” input = 2.0V.
DUAL DPST - DG184/185
TEST CONDITIONS
V_IN “ON” = 2.0V
All Channels
V_IN “OFF” = 0.8V
All Channels
NOTE:
1. Switch states are for logic “1” input = 2.0V.
SPDT - DG187/188
TEST CONDITIONS
V_IN “ON” = 2.0V
Channel 1
V_IN “ON” = 0.8V
Channel 2
V_IN “OFF” = 2.0V
Channel 2
V_IN “OFF” = 0.8V
Channel 1
NOTE:
1. Switch states are for logic “1” input = 2.0V.
SPDT - DG190/191
TEST CONDITIONS
V_IN “ON” = 2.0V
Channel 1 and 2
V_IN “ON” = 0.8V
Channel 3 and 4
V_IN “OFF” = 2.0V
Channel 3 and 4
V_IN “OFF” = 0.8V
Channel 1 and 2
NOTE:
1. Switch states are for logic “1” input = 2.0V.
Switching Time Test Circuits
LOGIC _3V
INPUT
t_R < 10ns
t_F < 10ns ^0V
SWITCH
INPUT
V_S
SWITCH _0V
OUTPUT
50%
90%
t _ON
50%
90%
t _OFF
+5V
V_L
SWITCH ^S1
INPUT
t_ON, V_S = +10V
t_OFF, V_S = -10V
IN₁
LOGIC
INPUT
GND
0V
+15V
V_CC
D₁
R_L
1kΩ
SWITCH
OUTPUT
V_O
C_L
30pF
(REPEAT TEST FOR
V-
-15V
ALL CHANNELS)
R_L
V_O = V_{S RL + RDS(ON)}
FIGURE 1. SWITCHING TIME TEST WAVEFORMS (Note 1)
FIGURE 2. SWITCHING TIME TEST CIRCUIT (Note 2)
NOTES:
1. Switch output waveform shown for V_S = constant with logic input waveform as shown.
2. V_S may be + or - as per switching time test circuit. V_O is the steady state output with switch on. Feedthrough via gate capacitance may
result in spikes at leading and trailing edge of output waveform.
6