CD4724BMS Datasheet, PDF (6/10 Pages) Intersil Corporation – CMOS 8-Bit Addressable Latch

Specifications CD4724BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 2
Note 1
OPEN
4 - 7, 9 - 12
GROUND
8
VDD
1 - 3, 13 - 16
9V ± -0.5V
50kHz
25kHz
Dynamic Burn-
-
In Note 1
1 - 3, 8
16
4 - 7, 9 - 12
14, 15
13
Irradiation
Note 2
4 - 7, 9 - 12
8
1 - 3, 13 - 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
*
A0 1
*
A1 2
*
A2 3
*
DATA 13
*
WRITE
DISABLE
14
*
RESET 15
VSS = 8
VDD = 16
A0
A1
A2
A0
A1
A2
A0
A0
A1
A2
A0
A0
A1
A1
A2
A1
A0
A1
A2
A2
A0
A1
A2
A2
A0
D
A1
A2
A0
A1
A2
WD
D
WD
LATCH
0
4 Q0
R
D
WD
LATCH
1
5 Q1
R
D
WD
LATCH
2
6 Q2
R
D
WD
LATCH
3
7 Q3
R
D
WD
LATCH
4
9 Q4
R
D
WD
LATCH
5
10 Q5
R
D
WD
LATCH
6
11 Q6
R
D
WD
LATCH
7
12 Q7
R
R
R
ADDRESS
WD
VDD
DATA
p
Q
n
*ALL INPUTS ARE
PROTECTED BY
VSS
p
COS/MOS PROTECTION
n
NETWORK
FIGURE 1. LOGIC DIAGRAM OF CD4724BMS AND DETAIL OF 1 OF 8 LATCHES
7-1272