CD4514BMS_06 Datasheet, PDF (6/9 Pages) Intersil Corporation – CMOS 4-Bit Latch/4-to-16 Line Decoders

CD4514BMS, CD4515BMS
Logic Diagram
VDD
VSS
*
DATA 1 2
*
DATA 2 3
*
DATA 3 21
*
DATA 4 22
*
STROBE 1
*
INHIBIT 23
A
SQ
RQ
B
SQ
RQ
S QC
RQ
D
SQ
RQ
ABCD
11 S0
ABCD
9 S1
ABCD
10 S2
ABCD
8 S3
ABCD
7 S4
ABCD
6 S5
ABCD
5 S6
ABCD
4 S7
ABCD
18 S8
ABCD
17 S9
ABCD
20 S10
ABCD
19 S11
ABCD
14 S12
ABCD
13 S13
ABCD
16 S14
ABCD
15 S15
* All inputs protected by CMOS protection network.
THESE INVENTERS USED ONLY ON CD4515BMS
FIGURE 1. LOGIC DIAGRAM
TRUTH TABLE
INHIBIT
DECODER INPUTS
DCBA
SELECTED OUTPUT
CD4514BMS = LOGIC 1 (HIGH)
CD4515BMS = LOGIC 0 (LOW)
0
0000
S0
0
0001
S1
0
0010
S2
0
0011
S3
0
0100
S4
0
0101
S5
0
0110
S6
0
0111
S7
0
1000
S8
0
1001
S9
0
1010
S10
0
1011
S11
0
1100
S12
0
1101
S13
0
1110
S14
0
1111
S15
1
X X X X All Outputs = 0, CD4514BMS
All Outputs = 1, CD4515BMS
1 = HIGH LEVEL
0 = LOW LEVEL X = DON’T CARE
6