CD4043BMS Datasheet, PDF (6/10 Pages) Intersil Corporation – CMOS Quad Clocked “D” Latch

Specifications CD4043BMS, CD4044BMS
Functional Diagram
S1 4
R1 3
VDD
16
LATCH
1
2 Q1
R1 4
S1 3
VDD
16
LATCH
1
S2 6
R2 7
LATCH
2
9 Q2
R2 6
S2 7
LATCH
2
S3 12
R3 11
LATCH
3
10 Q3
R3 12
S3 11
LATCH
3
S4 14
R4 15
ENABLE 5
LATCH
4
8
VSS
CD4043BMS
1 Q4
13 NC
R4 14
S4 15
ENABLE 5
LATCH
4
8
VSS
CD4044BMS
13 Q1
9 Q2
10 Q3
1 Q4
2 NC
Logic Diagram
S1
*4
EQUIVALENT
NOR LATCH
R1
*³
E
*⁵
VDD
E
VDD
Q1
2
E
E
VSS
E
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
S1
*3
EQUIVALENT
NAND LATCH
R1
*⁴
E
*⁵
VDD
E
VDD
Q1
13
E
E
VSS
E
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
CD4043BMS
CD4043BMS
S
R
E
X
X
O
O
O
1
1
O
1
O
1
1
1
1
1
* Open Circuit
** No Change
∆ Dominated by S = 1 input
Q
OC*
NC**
1
O
∆
TRUTH TABLE
VSS
CD4044BMS
CD4044BMS
S
R
E
X
X
O
1
1
1
O
1
1
1
O
1
O
O
1
* Open Circuit
** No Change
∆∆ Dominated by R = O input
Q
OC*
NC**
1
O
∆∆
7-881