CD40109BMS Datasheet, PDF (6/9 Pages) Intersil Corporation – CMOS Quad Low-to-High Voltage Level Shifter

Specifications CD40109BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
5005
TEST
PRE-IRRAD
POST-IRRAD
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 (Note 1) 4, 5, 11-13 2, 3, 6-10, 14, 15
1, 16
Static Burn-In 2 (Note 1) 4, 5, 11-13
8
16
1-3, 4, 7, 9, 10,
14, 15
Dynamic Burn-In (Note 4)
12
8
16
1, 4, 5, 11, 13
3, 6, 10, 14
2, 7, 9, 15
(Note 3)
(Note 3)
Irradiation (Note 2)
4, 5, 11-13
8
1-3, 6, 7, 9, 10,
14-16
NOTES:
1. Each pin except Pin 1, VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except Pin 1, VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
3. Pin voltage is VDD/2
4. Each pin except Pin 1, VDD and GND will have a series resistor of 4.75K ±5%, VDD = 18V ±0.5V.
Logic Diagram
VCC
VDD
A^*
3 (6, 10, 14)
LEVEL
SHIFTER
ENABLE A ^*
2 (7, 9, 15)
LEVEL
SHIFTER
VDD
VDD
E
4 (5, 11, 13)
VCC = 1
VDD = 16
VSS = 8
VSS
* ^{ALL INPUTS ARE PROTECTED}
BY CMOS PROTECTION
NETWORK
VSS
FIGURE 1. 1 OF 4 UNITS
TRUTH TABLE
INPUTS
OUTPUTS
A, B, C, D
ENABLE
A, B, C, D
E, F, G, H
0
1
0
1
1
1
X
0
Z
Logic 0 = Low(VSS)
X = Don’t care
Z = High impedance
Logic 1 = VCC at Inputs and VDD at Outputs
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