CD40107BMS Datasheet, PDF (6/7 Pages) Intersil Corporation – CMOS Dual 2 Input NAND Buffer/Driver

Schematic
VDD
A^*
3, (11)
B^*
4, (10)
NOTE:
VSS
1 OF 2 GATES (NUMBERS IN PARENTHESES
ARE TERMINAL NUMBERS FOR SECOND GATE)
CD40107BMS
VDD
* ^{ALL INPUTS ARE PROTECTED}
BY CMOS PROTECTION
NETWORK
C=A• B
5, (9)
VSS
VDD = 14
VSS = 7
TRUTH TABLE
A
B
C
0
0
1*
Z**
1
0
1*
Z**
0
1
1*
Z**
1
1
0
* Requires external pull-up resistor (RL)
to VDD.
** Without pull-up resistor (3-state).
FIGURE 1. 1 OF 2 GATES
Typical Performance Characteristics
AMBIENT TEMPERATURE (T_A) = +25^oC
AMBIENT TEMPERATURE (T_A) = +25^oC
960
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
800
640
480
10V
320
160
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
80
AMBIENT TEMPERATURE (T_A) = +25^oC
70 RL = 120Ω TO VDD
60
SUPPLY VOLTAGE (VDD) = 5V tTLH
50
5V tTHL
40
30
20
10
10V tTLH
15V tTLH
10V tTHL
15V tTHL
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (CL) (pF)
FIGURE 4. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
480
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
400
320
10V
240
160
80
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (T_A) = +25^oC
175 RL = 120Ω TO VDD
150
125
SUPPLY VOLTAGE (VDD) = 5V tPLH, tPHL
100
75
15V tPLH
50
25
10V tPHL
10V tPLH
10V TPHL
15V tPHL
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (CL) (pF)
FIGURE 5. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
7-23