82C89_06 Datasheet, PDF (6/13 Pages) Intersil Corporation – CMOS Bus Arbiter

82C89
X1
X2
RDY2
82C84A/85
CLOCK
GENERATOR
AEN2
READY ^RDY1
CLK AEN1
V_CC
READY
CLK
80C86
CPU
S0
AD0-AD15 ^S1
A16-A19 S2
STATUS (S0, S1, S2)
PROCESSOR
LOCAL BUS
OE STB
ADDRESS
LATCH
82C82/
82C83H
(2 OR 3)
OE DT/R
TRANSCEIVER
82C86H/
82C87H
(2)
82C89
BUS
ARBITER
ANYRQST
CLK
IOB
S0-S2 RESB
AEN
XACK MULTI-MASTER
SYSTEM BUS
MULTI-MASTER
CONTROL BUS
V_CC
AEN
82C88
BUS
CONTROLLER
CLK
ALE
IOB
DEN DT/R
XCVR
DISABLE
MULTI-MASTER SYSTEM
COMMAND BUS
MULTI-MASTER SYSTEM
ADDRESS BUS
MULTI-MASTER SYSTEM
DATA BUS
FIGURE 4. TYPICAL MEDIUM COMPLEXITY CPU SYSTEM
6
FN2980.2
February 27, 2006