82C89_06 Datasheet, PDF (3/13 Pages) Intersil Corporation – CMOS Bus Arbiter

82C89
Pin Description (Continued)
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
SYSB/RESB
3
I SYSTEM BUS/RESIDENT BUS: An input signal when the arbiter is configured in the System/Resident Mode
(RESB is strapped high) which determines when the multi-master system bus is requested and multi-master
system bus surrendering is permitted. The signal is intended to originate from a form of address-mapping
circuitry, such as a decoder or PROM attached to the resident address bus. Signal transitions and glitches are
permitted on this pin from θ1 of T4 to θ1 of T2 of the processor cycle. During the period from θ1 of T2 to θ1 of T4,
only clean transitions are permitted on this pin (no glitches). If a glitch occurs, the arbiter may capture or miss it,
and the multi-master system bus may be requested or surrendered, depending upon the state of the glitch. The
arbiter requests the multi-master system bus in the System/Resident Mode when the state of the SYSB/RESB
pin is high and permits the bus to be surrendered when this pin is low.
CBRQ
12
I/O COMMON BUS REQUEST: An input signal which instructs the arbiter if there are any other arbiters of lower
priority requesting the use of the multi-master system bus.
The CBRQ pins (open-drain output) of all the 82C89 Bus Arbiters which surrender to the multi-master system
bus upon request are connected together.
The Bus Arbiter running the current transfer cycle will not itself pull the CBRQ line low. Any other arbiter
connected to the CDRQ line can request the multi-master system bus. The arbiter presently running the current
transfer cycle drops its BREQ signal and surrenders the bus whenever the proper surrender conditions exist.
Strapping CBRQ low and ANYRQST high allows the multi-master system bus to be surrendered after each
transfer cycle. See the pin definition of ANYRQST.
BCLK
5
I BUS CLOCK: The multi-master system bus clock to which all multi-master system bus interface signals are
synchronized.
BREQ
7
O BUS REQUEST: An active low output signal in the Parallel Priority Resolving Scheme which the arbiter activates
to request the use of the multi-master system bus.
BPRN
9
I BUS PRIORITY IN: The active low signal returned to the arbiter to instruct it that it may acquire the multi-master
system bus on the next falling edge of BCLK. BPRN active indicates to the arbiter that it is the highest priority
requesting arbiter presently on the bus. The loss of BPRN instructs the arbiter that it has lost priority to a higher
priority arbiter.
BPRO
8
O BUS PRIORITY OUT: An active low output signal used in the serial priority resolving scheme where BPRO is
daisy-chained to BPRN of the next lower priority arbiter.
BUSY
11
I/O BUSY: An active low open-drain multi-master system bus interface signal used to instruct all the arbiters on the
bus when the multi-master system bus is available. When the multi-master system bus is available the highest
requesting arbiter (determined by BPRN) seizes the bus and pulls BUSY low to keep other arbiters off of the bus.
When the arbiter is done with the bus, it releases the BUSY signal, permitting it to go high and thereby allowing
another arbiter to acquire the multi-master system bus.
Functional Description
The 82C89 Bus Arbiter operates in conjunction with the
82C88 Bus Controller to interface 80C86, 80C88 processors
to a multi-master system bus (both the 80C86 and 80C88 are
configured in their max mode). The processor is unaware of
the arbiter’s existence and issues commands as though it
has exclusive use of the system bus. If the processor does
not have the use of the multi-master system bus, the arbiter
prevents the Bus Controller (82C88), the data transceivers
and the address latches from accessing the system bus (e.g.
all bus driver outputs are forced into the high impedance
state). Since the command sequence was not issued by the
82C88, the system bus will appear as “Not Ready” and the
processor will enter wait states. The processor will remain in
Wait until the Bus Arbiter acquires the use of the multi-master
system bus whereupon the arbiter will allow the bus controller,
the data transceivers, and the address latches to access the
system. Typically, once the command has been issued and a
data transfer has taken place, a transfer acknowledge (XACK)
is returned to the processor to indicate “READY” from the
accessed slave device. The processor then completes its
transfer cycle. Thus the arbiter serves to multiplex a processor
(or bus master) onto a multi-master system bus and avoid
contention problems between bus masters.
Arbitration Between Bus Masters
In general, higher priority masters obtain the bus when a
lower priority master completes its present transfer cycle.
Lower priority bus masters obtain the bus when a higher
priority master is not accessing the system bus. A strapping
option (ANYRQST) is provided to allow the arbiter to
surrender the bus to a lower priority master as though it were
a master of higher priority. If there are no other bus masters
requesting the bus, the arbiter maintains the bus so long as
its processor has not entered the HALT State. The arbiter will
not voluntarily surrender the system bus and has to be forced
off by another master’s bus request, the HALT State being the
only exception. Additional strapping options permit other
modes of operation wherein the multi-master system bus is
surrendered or requested under different sets of conditions.
3
FN2980.2
February 27, 2006