82C84A Datasheet, PDF (6/10 Pages) Intersil Corporation – CMOS Clock Generator Driver

82C84A
AC Electrical Specifications
V_CC = +5V± 10%,
T_A = 0^oC to +70^oC (C82C84A),
T_A = -40^oC to +85^oC (I82C84A),
T_A = -55^oC to +125^oC (M82C84A)
SYMBOL
PARAMETER
LIMITS
MIN
MAX
UNITS
(NOTE 1)
TEST
CONDITIONS
TIMING REQUIREMENTS
(1) TEHEL
(2) TELEH
(3) TELEL
External Frequency HIGH Time
External Frequency LOW Time
EFI Period
13
-
ns
90%-90% V_IN
13
-
ns
10%-10% V_IN
36
-
ns
XTAL Frequency
2.4
25
MHz Note 2
(4) TR2VCL
RDY1, RDY2 Active Setup to CLK
35
-
ns
ASYNC = HIGH
(5) TR1VCH
RDY1, RDY2 Active Setup to CLK
35
-
ns
ASYNC = LOW
(6) TR1VCL
RDY1, RDY2 Inactive Setup to CLK
35
-
ns
(7) TCLR1X
RDY1, RDY2 Hold to CLK
0
-
ns
(8) TAYVCL
ASYNC Setup to CLK
50
-
ns
(9) TCLAYX
ASYNC Hold to CLK
0
-
ns
(10) TA1VR1V
AEN1, AEN2 Setup to RDY1, RDY2
15
-
ns
(11) TCLA1X
AEN1, AEN2 Hold to CLK
0
-
ns
(12) TYHEH
CSYNC Setup to EFI
20
-
ns
(13) TEHYL
CSYNC Hold to EFI
20
-
ns
(14) TYHYL
CSYNC Width
2 TELEL
-
ns
(15) TI1HCL
(16) TCLI1H
TIMING RESPONSES
(17) TCLCL
(18) TCHCL
(19) TCLCH
(20) TCH1CH2
(21) TCL2CL1
RES Setup to CLK
RES Hold to CLK
CLK Cycle Period
CLK HIGH Time
CLK LOW Time
CLK Rise or Fall Time
65
-
20
-
125
-
(1/3 TCLCL) +2.0
-
(2/3 TCLCL) -15.0
-
-
10
ns
Note 3
ns
Note 3
ns
Note 6
ns
Note 6
ns
Note 6
ns
1.0V to 3.0V
(22) TPHPL
PCLK HIGH Time
TCLCL-20
-
ns
Note 6
(23) TPLPH
PCLK LOW Time
TCLCL-20
-
ns
Note 6
(24) TRYLCL
Ready Inactive to CLK (See Note 4)
-8
-
ns
Note 4
(25) TRYHCH
Ready Active to CLK (See Note 3)
(2/3 TCLCL) -15.0
-
ns
Note 5
(26) TCLIL
CLK to Reset Delay
-
40
ns
(27) TCLPH
CLK to PCLK HIGH Delay
-
22
ns
(28) TCLPL
CLK to PCLK LOW Delay
-
22
ns
(29) TOLCH
OSC to CLK HIGH Delay
-5
22
ns
(30) TOLCL
OSC to CLK LOW Delay
2
35
ns
NOTES:
1. Tested as follows: f = 2.4MHz, V_IH = 2.6V, V_IL = 0.4V, C_L = 50pF, V_OH ≥ 1.5V, V_OL ≤ 1.5V, unless otherwise specified. RES and F/C must
switch between 0.4V and V_CC -0.4V. Input rise and fall times driven at 1ns/V. V_IL ≤ V_IL (max) - 0.4V for CSYNC pin. V_CC = 4.5V and 5.5V.
2. Tested using EFI or X1 input pin.
3. Setup and hold necessary only to guarantee recognition at next clock.
4. Applies only to T2 states.
5. Applies only to T3 TW states.
6. Tested with EFI input frequency = 4.2MHz.
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