X98027_06 Datasheet, PDF (5/29 Pages) Intersil Corporation – 275MHz Triple Video Digitizer with Digital PLL

X98027
Electrical Specifications Specifications apply for V_A = V_D = V_X = 3.3V, pixel rate = 275MHz, f_XTAL = 25MHz, T_A = 25°C,
unless otherwise noted (Continued)
SYMBOL
PARAMETER
COMMENT
MIN
TYP
MAX
t_HOLD DATA valid after rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
2.0
(Note 1)
AC TIMING CHARACTERISTICS (2 WIRE INTERFACE)
f_SCL
SCL Clock Frequency
Maximum width of a glitch on SCL that will 2 XTAL periods min
be suppressed
0
400
80
t_AA SCL LOW to SDA Data Out Valid
5 XTAL periods plus SDA’s RC time
constant
See
comment
t_BUF Time the bus must be free before a new
1.3
transmission can start
t_LOW Clock LOW Time
1.3
t_HIGH Clock HIGH Time
0.6
t_SU:STA Start Condition Setup Time
0.6
t_HD:STA Start Condition Hold Time
0.6
t_SU:DAT Data In Setup Time
100
t_HD:DAT Data In Hold Time
0
t_SU:STO Stop Condition Setup Time
0.6
t_DH Data Output Hold Time
4 XTAL periods min
160
NOTES:
1. Setup and hold times are at a 140MHz DATACLK rate.
2. See Table 8 on page 24.
UNIT
ns
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
SCL
SDA IN
t_SU:ST
SDA OUT
t_F
t_HIGH
t_SU:DAT
t_HD:STA
t_LOW
t_HD:DAT
t_R
t_AA t_DH
FIGURE 1. 2 WIRE INTERFACE TIMING
t_SU:STO
t_BUF
DATACLK
DATACLK
Pixel Data
t_SETUP
t_HOLD
FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING
5
FN8221.3
March 8, 2006