X98027_06 Datasheet, PDF (26/29 Pages) Intersil Corporation – 275MHz Triple Video Digitizer with Digital PLL

X98027
Communication is accomplished in three steps:
1. The Host selects the X98027 it wishes to communicate
with.
2. The Host writes the initial X98027 Configuration Register
address it wishes to write to or read from.
3. The Host writes to or reads from the X98027’s
Configuration Register. The X98027’s internal address
pointer auto increments, so to read registers 0x00
through 0x1B, for example, one would write 0x00 in step
2, then repeat step 3 28 times, with each read returning
the next register value.
The X98027 has a 7 bit address on the serial bus. The upper
6 bits are permanently set to 100110, with the lower bit
determined by the state of pin 48. This allows 2 X98027s to
be independently controlled while sharing the same bus.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 12).
The X98027 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command
until this condition has been met. The host then transmits the
7 bit serial address plus a R/W bit, indicating if the next
transaction will be a Read (R/W = 1) or a Write (R/W = 0). If
the address transmitted matches that of any device on the
bus, that device must respond with an ACKNOWLEDGE
(Figure 13).
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be
written to or read from the slave. Communication with the
selected device in the selected direction (read or write) is
ended by a STOP command, where SDA rises while SCL is
high (Figure 12), or a second START command, which is
commonly used to reverse data direction without
relinquishing the bus.
Data on the serial bus must be valid for the entire time SCL
is high (Figure 14). To achieve this, data being written to the
X98027 is latched on a delayed version of the rising edge of
SCL. SCL is delayed and deglitched inside the X98027 for 3
crystal clock periods (120ns for a 25MHz crystal) to eliminate
spurious clock pulses that could disrupt serial
communication.
When the contents of the X98027 are being read, the SDA
line is updated after the falling edge of SCL, delayed and
deglitched in the same manner.
Configuration Register Write
Figure 15 shows two views of the steps necessary to write
one or more words to the Configuration Register.
Configuration Register Read
Figure 16 shows two views of the steps necessary to read
one or more words from the Configuration Register.
SCL
SDA
Start
Stop
FIGURE 12. VALID START AND STOP CONDITIONS
SCL from
Host
1
Data Output
from Transmitter
8
9
Data Output
from Receiver
Start
Acknowledge
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
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FN8221.3
March 8, 2006