X9420_06 Datasheet, PDF (5/19 Pages) Intersil Corporation – Single Digitally Controlled Potentiometer

X9420
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
Serial
V_H
From Interface
Circuitry
Bus
Input
C
Register 0
Register 1
O
U
8
6
Parallel
Bus
Input
N
T
E
R
REGISTER 2
REGISTER 3
Wiper
D
Counter
E
Register
C
(WCR)
O
D
E
INC/DEC
IF WCR = 00[H] THEN V_W = V_L
IF WCR = 3F[H] THEN V_W = V_H
UP/DN
Logic
UP/DN
Modified SCK
CLK
V_L
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.
INSTRUCTIONS
Address/Identification (ID) Byte
The first byte sent to the X9420 from the host,
following a CS going HIGH to LOW, is called the
Address or Identification byte. The most significant
four bits of the slave address are a device type
identifier, for the X9420 this is fixed as 0101[B] (refer
to Figure 2).
The least significant bit in the ID byte selects one of
two devices on the bus. The physical device address
is defined by the state of the A₀ input pin. The X9420
compares the serial data stream with the address
input state; a successful compare of the address bit is
required for the X9420 to successfully continue the
command sequence. The A₀ input can be actively
driven by a CMOS input signal or tied to V_CC or V_SS.
The remaining three bits in the ID byte must be set to 110.
V_W
Figure 2. Address/Identification Byte Format
Device Type
Identifier
0 1 0 1 _{1 1 0 A0}
Device Address
Instruction Byte
The next byte sent to the X9420 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next two
bits point to one of four data registers. The format is
shown below in Figure 3.
Figure 3. Instruction Byte Format
Register
Select
I3 I2 I1 I0 R1 R0 0
0
Instructions
5
FN8195.1
April 26, 2006