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X9420_06 Datasheet, PDF (12/19 Pages) Intersil Corporation – Single Digitally Controlled Potentiometer
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X9420
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Symbol
Parameter
ICC1 VCC Supply Current (Active)
ICC2
ISB
ILI
ILO
VIH
VIL
VOL
VCC Supply Current
(Non-volatile Write)
VCC Current (Standby)
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
Output LOW Voltage
Min.
Limits
Typ. Max.
400
1
VCC x 0.7
-0.5
1
10
10
VCC + 0.5
VCC x 0.1
0.4
Units
µA
mA
μA
μA
μA
V
V
V
Test Conditions
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
SCK = SI = VSS, Addr. = VSS
VIN = VSS to VCC
VOUT = VSS to VCC
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Minimum Endurance
Data Retention
Min.
100,000
100
Units
Data Changes per Bit per Register
Years
CAPACITANCE
Symbol
COUT(5)
CIN(5)
Test
Output Capacitance (SO)
Input Capacitance (A0, SI, and SCK)
Max.
8
6
Units
pF
pF
Test Conditions
VOUT = 0V
VIN = 0V
POWER-UP TIMING
Symbol
tPUR(6)
tPUW(6)
tRVCC
Parameter
Power-up to Initiation of Read Operation
Power-up to Initiation of Write Operation
VCC Power-up Ramp
Max.
1
5
0.2
Max.
1
5
50
Units
ms
ms
V/msec
POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then V+ and V-, and then the potentiometer pins, RH, RL,
and RW. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The VCC ramp rate
specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible.
If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for
proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will not
be complete until VCC, V+ and V- reach their final value.
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction
can be issued. These parameters are periodically sampled and not 100% tested.
12
FN8195.1
April 26, 2006
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