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X9401 Datasheet, PDF (5/20 Pages) Intersil Corporation – Low Noise/Low Power/SPI Bus
Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
From Interface
Circuitry
Register 0
8
Register 2
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
X9401
Serial
Bus
Input
C
Register 1
o
u
6
Parallel
Bus
Input
n
t
e
r
Register 3
Wiper
Counter
D
Register
e
(WCR)
c
o
d
e
UP/DN
INC/DEC
Logic
UP/DN
Modified SCL
CLK
VH/RH
VL/RL
Write in Process
The contents of the Data Registers are saved to non-
volatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a Write In Process bit (WIP).
The WIP bit is read with a Read Status command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9401 from the host, follow-
ing a CS going HIGH to LOW, is called the Identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9401 this
is fixed as 0101[B] (refer to Figure 1).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0 - A1 input
pins. The X9401 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9401 to successfully
continue the command sequence. The A0 - A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
5
Figure 1. Identification Byte Format
Device Type
Identifier
VW/RW
0 1 0 1 0 0 A1 A0
Device Address
Instruction Byte
The next byte sent to the X9401 contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable,
they point to one of four associated registers. The for-
mat is shown below in Figure 2.
FN8190.2
September 23, 2005