X9241A_15 Datasheet, PDF (5/17 Pages) Intersil Corporation – Non-Volatile/Low Power/2-Wire/64 Taps

X9241A
of the wiper to this action will be delayed t_STPWV. A transfer
from WCR current wiper position to a Data Register is a write
to nonvolatile memory and takes a minimum of t_WR to
complete. The transfer can occur between one of the four
potentiometers and one of its associated registers; or it may
occur globally, wherein the transfer occurs between all four of
the potentiometers and one of their associated registers.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9241A; either between the host and one of the Data
Registers or directly between the host and the WCR. These
instructions are: Read WCR, read the current wiper position
of the selected pot; Write WCR, change current wiper
position of the selected pot; Read Data Register, read the
contents of the selected nonvolatile register; Write Data
SCL
Register, write a new value to the selected Data Register.
The sequence of operations is shown in Figure 4.
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9241A has responded with an acknowledge, the master
can clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t_HIGH) while SDA is HIGH, the
selected wiper will move one resistor segment towards the
V_H/R_H terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V_L/R_L terminal. A detailed illustration
of the sequence and timing for this operation is shown in
Figures 5 and 6 respectively.
SDA
S 0 1 0 1 A3 A2 A1 A0 _A I3 I2 I1 I0 P1 P0 R1 R0 A S
T
C
CT
A
K
KO
R
P
T
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S0
T
A
R
T
10
1 A3 A2 A1 A0 A I3 I2
C
K
I1 I0 P1 P0 R1 R0 A CM DW D5 D4 D3 D2 D1 D0 A S
C
CT
K
KO
P
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
SCL
SDA
XX
S 0 1 0 1 A3 A2 A1 A0 A I3 I2 I1 I0 P1 P0 R1 R0 A I
I
T
C
CN _N
A
K
KC _C
R
12
T
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
ID
NE
CC
n1
DS
ET
CO
nP
5
FN8164.7
August 17, 2015