RFD10P03L Datasheet, PDF (5/8 Pages) Fairchild Semiconductor – 10A, 30V, 0.200W, Logic Level P-Channel Power MOSFET

RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves Unless Otherwise Specified (Continued)
1.2
V_GS = V_DS, I_D = -250µA
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
160 200
T_J, JUNCTION TEMPERATURE (^oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
-30
-22.5
V_DD =BV_DSS
V_DD = BV_DSS
-5.00
-3.75
R_L = 3.0Ω
-15
I_G(REF) = -0.25mA
-2.50
0.75 BV_{DSS 0.75 BVDSS}
0.50 BV_DSS 0.50 BV_DSS
-7.5
0.25 BV_DSS 0.25 BV_DSS
-1.25
V_GS = -5V
0
I_G(REF)
20
I_G(ACT)
t, TIME ( µs)
I_G(REF)
80
I_G(ACT)
0.00
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
150
V_DD = -15V, I_D = -10A, R_L= 1.50Ω
125
100
75
50
25
t_r
t_d(OFF)
t_f
t_d(ON)
0
0
10
20
30
40
50
R_GS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 13. SWITCHING TIME vs GATE RESISTANCE
1200
1000
800
600
400
200
0
0
C_ISS
C_OSS
V_GS = 0V, f = 0.1MHz
C_ISS = C_GS + C_GD
C_RSS = C_GD
C_OSS ≈ C_DS + C_GD
C_RSS
-5
-10
-15
-20
-25
V_DS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 15. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VARY t_P TO OBTAIN
REQUIRED PEAK I_AS
R_G
0V
V_GS
t_P
V_DS
L
DUT
-
V_DD
+
I_AS
0.01Ω
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
t_AV
0
V_DD
I_AS
t_P
BV_DSS
V_DS
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
7-7