ISLA110P50_11 Datasheet, PDF (5/34 Pages) Intersil Corporation – 10-Bit, 500MSPS A/D Converter

ISLA110P50
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Resistance (Typical)
θ_JA (°C/W) θ_JC (°C/W)
72 Ld QFN (Notes 3, 4, 5) . . . . . . . . . . . . . .
23
0.75
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
NOTES:
3. θ_JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
4. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.
5. For solder stencil layout and reflow guidelines, please see Tech Brief TB389.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T_A = -40°C to +85°C (typical specifications at +25°C), A_IN = -1dBFS, F_IN = 105MHz, f_SAMPLE = 500MSPS, after completion of I2E calibration.
ISLA110P50
(Note 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input Range
Input Resistance
Input Capacitance
Full Scale Range Temp. Drift
Input Offset Voltage
Gain Error
Common-Mode Output Voltage
Clock Inputs
V_FS
R_IN
C_IN
A_VTC
V_OS
E_G
V_CM
Differential
Differential
Differential
Full Temp
1.41
-10
435
1.45
500
1.9
325
±2.0
±2.0
535
1.52
10
635
V_P-P
Ω
pF
ppm/°C
mV
%
mV
Inputs Common Mode Voltage
0.9
V
CLKP, CLKN Input Swing
0.2
1.8
V
Power Requirements
1.8V Analog Supply Voltage
AVDD
1.7
1.8
1.9
V
1.8V Digital Supply Voltage
OVDD
1.7
1.8
1.9
V
1.8V Analog Supply Current
IAVDD
173
186
mA
1.8V Digital Supply Current (Note 7)
I_OVDD
3mA LVDS, I2E powered down, Notch
Filter powered down
79
86
mA
3mA LVDS, I2E On, Notch Filter On
124
mA
Power Supply Rejection Ratio
Total Power Dissipation
PSRR
30MHz, 200mV_P-P
-36
dB
Normal Mode
P_D
2mA LVDS, I2E powered down, Notch
441
mW
Filter powered down
3mA LVDS, I2E powered down, Notch
Filter powered down
454
490
mW
3mA LVDS, I2E On, Notch Filter powered
520
mW
down
3mA LVDS, I2E On, Notch Filter On
535
mW
Nap Mode
P_D
164
179
mW
5
FN7606.2
July 25, 2011