ISL8272M Datasheet, PDF (5/55 Pages) Intersil Corporation – 50A Digital DC/DC PMBus Power Module

ISL8272M
Pin Descriptions (Continued)
PIN
LABEL TYPE
DESCRIPTION
C12
SDA I/O Serial data. Connect to external host and/or to other Digital-DC™ devices. A pull-up resistor is required.
C13
SCL I/O Serial clock. Connect to external host and/or to other Digital-DC™ devices. A pull-up resistor is required.
D4
SS/
I Soft-start/stop and undervoltage lockout selection pin. Used to set turn on/off delay and ramp time as well as input
UVLO
UVLO threshold levels.
D5
PG
O Power-good output. Power-good output can be an open drain that requires a pull-up resistor or push-pull output that
can drive a logic input.
D13
SYNC I/O Clock synchronization input. Used to set the frequency of the internal switch clock, to sync to an external clock or to
output internal clock.
E14
EN
I Enable pin. Logic high to enable the module output.
E4
DDC I/O A Digital-DC bus. This dedicated bus provides the communication between devices for features such as sequencing,
fault spreading and current sharing. The DDC pin on all Digital-DC devices should be connected together. A pull-up
resistor is required.
C5, D14, E15, TEST
F4, F15, G4
- Test pins. Don’t connect these pins.
G14
ASCR I ChargeMode™ control ASCR parameters selection pin. Used to set ASCR gain and residual values.
G15
V25 PWR Internal 2.5V reference used to power internal circuitry. No external capacitor required for this pin.
H3
VSENN I Differential output voltage sense feedback. Connect to negative output regulation point.
H4
VSENP I Differential output voltage sense feedback. Connect to positive output regulation point.
H16, J16, K16, SGND PWR Signal grounds. Using multiple vias to connect the SGND pins to the internal SGND layer.
M14
K14
VDD PWR Input supply voltage for controller. Connect VDD pad to VIN supply.
L2
VR PWR Internal LDO bias pin. Tie VR to VR55 directly with a short loop trace.
L3, P11
SWD1, PWR Switching node driving pins. Directly connect to the SW1 and SW2 pads with short loop wires.
SWD2
L14
VR5 PWR Internal 5V reference used to power internal circuitry. Place a 10µF decoupling capacitor for this pin.
M1
VCC PWR Internal LDO output. Connect VCC to VDRV for internal LDO driving.
M5, M17, N5 PGND PWR Power grounds. Using multiple vias to connect the PGND pins to the internal PGND layer.
M10
VR55 PWR Internal 5.5V bias voltage for internal LDO use only. Tie VR55 pin directly to VR pin.
M13
VR6 PWR Internal 6V reference used to power internal circuitry. Place a 10µF decoupling capacitor for this pin.
N6, N16
VDRV
PWR Power supply for internal FET drivers. Connect 10μF bypass capacitor to each of these pins. These pins can be driven
by the internal LDO through VCC pin or by the external power supply directly. Keep the driving voltage between 4.5V
and 5.5V. For 5V input application, use external supply or connect this pin to VIN.
R8, R17 VDRV1 I Bias pin of the internal FET drivers. Always tie to VDRV.
Submit Document Feedback
5
FN8670.2
January 14, 2015