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ISL8272M Datasheet, PDF (27/55 Pages) Intersil Corporation – 50A Digital DC/DC PMBus Power Module
ISL8272M
PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA DEFAULT
FORMAT VALUE
DEFAULT
SETTING
PAGE
94h READ_DUTY_CYCLE
Returns the duty cycle reading READ WORD L11
41
during the ENABLE state.
95h READ_FREQUENCY
Returns the measured operating READ WORD L11
41
switch frequency.
96h READ_IOUT_0
Returns phase 1 current reading. READ WORD L11
41
97h READ_IOUT_1
Returns phase 2 current reading. READ WORD L11
42
99h MFR_ID
Sets a user defined identification. R/W BLOCK ASC
Null
42
9Ah MFR_MODEL
Sets a user defined model.
R/W BLOCK ASC
Null
42
9Bh MFR_REVISION
Sets a user defined revision.
R/W BLOCK ASC
Null
42
9Ch MFR_LOCATION
Sets a user defined location
identifier.
R/W BLOCK ASC
Null
42
9Dh MFR_DATE
Sets a user defined date.
R/W BLOCK ASC
Null
43
9Eh MFR_SERIAL
Sets a user defined serialized
identifier.
R/W BLOCK ASC
Null
43
A8H LEGACY_FAULT_GROUP
Sets rail IDs of legacy devices for R/W BLOCK BIT 00000000h No rail ID
43
fault spreading
specified
B0h USER_DATA_00
Sets a user defined data.
R/W BLOCK ASC
Null
43
D0h ISENSE_CONFIG
Configures ISENSE related
features.
R/W BYTE BIT
05h 256ns Blanking 44
Time, Mid Range
D1h USER_CONFIG
Configures several user-level
features.
R/W BYTE BIT
Pin Strap (ASCR 44
on/off for start
up)
D3h DDC_CONFIG
Configures the DDC bus.
R/W WORD BIT
Pin Strap (set
45
based on PMBus
address and CS)
D4h POWER_GOOD_DELAY
Sets the delay between VOUT > PG R/W WORD L11
C300h 3ms
45
threshold and asserting the PG
pin.
DFh ASCR_CONFIG
Configures ASCR control loop.
R/W BLOCK CUS
Pin Strap
45
E0h SEQUENCE
Identifies the Rail DDC ID to
perform multi-rail sequencing.
R/W WORD BIT
0000h Prequel and
46
Sequel Disabled
E2h DDC_GROUP
Sets rail DDC IDs to obey faults
and margining spreading
information.
R/W BLOCK BIT
Pin Strap (set
46
based on CS)
E4h DEVICE_ID
Returns the 16-byte (character)
device identifier string.
READ BLOCK ASC
Reads Device
47
Version
E5h MFR_IOUT_OC_FAULT_RESPONSE Configures the IOUT overcurrent
R/W BYTE
BIT
80h Disable and
47
fault response.
No Retry
E6h
MFR_IOUT_UC_FAULT_RESPONSE Configures the IOUT undercurrent R/W BYTE
BIT
80h Disable and
47
fault response.
No Retry
E9h SYNC_CONFIG
Configures the Sync pin.
R/W BYTE BIT
Pin Strap (set
47
based on CS)
EAh SNAPSHOT
Returns 32-byte read-back of
READ BLOCK BIT
48
parametric and status values.
EBh BLANK_PARAMS
Returns recently changed
READ BLOCK BIT
FF...FFh
48
parameter values.
F3h SNAPSHOT_CONTROL
Snapshot feature control
R/W BYTE BIT
48
command.
F4h RESTORE_FACTORY
Restores device to the factory
SEND BYTE
49
default values.
F5h MFR_VMON_OV_FAULT_LIMIT
Returns the VMON overvoltage READ WORD L11
CB00h 6V
49
threshold.
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FN8670.2
January 14, 2015