ISL6506BIBZ Datasheet, PDF (5/8 Pages) Intersil Corporation – Multiple Linear Power Controller with ACPI Control Interface

ISL6506BIBZ
initiation of soft-start. The 3.3V_DUAL rail is brought up
through the internal standby LDO through an internal digital
soft-start function. Figure 3 shows the 5V_DUAL rail initiating a
soft-start at time t2 as well.
At time t4, the system has transitioned into S0 state and the
ATX supplies have begun to ramp-up. With the ISL6506BIBZ
(Figure 2), the 5V_DUAL rail will begin to ramp-up from the
5V_ATX rail through the body diode of the N-MOSFET (Q₃). At
time t5, the 12V_ATX rail has surpassed the 12V POR level.
Time t6 is three soft-start cycles after the 12V POR level has
been surpassed. At time t6, three events occur
simultaneously. The DLA pin is forced to a high impedance
state which allows the 12V rail to enhance the two N-
MOSFETs (Q₁ and Q₃) that connect the ATX rails to the
3.3V_DUAL and 5V_DUAL rails. The 5VDLSB pin is actively
pulled high, which will turn the P-MOSFET (Q₂) off. Finally,
the internal LDO which regulates the 3.3V_AUX rail in sleep
states is put in standby mode.
5VSB
(1V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
3.3VDUAL
(2V/DIV)
5VDUAL
(1V/DIV)
0V
DLA
(10V/DIV)
t0 t1 t2 t3
t4 t5
t6
TIME
FIGURE 2. ISL6506BIBZ SOFT-START INTERVAL IN S4/S5
STATE AND S5 TO S0 TRANSITION
Sleep to Wake State Transitions
Figures 2 and 3, starting at time t4, depict the transitions
from sleep states to the S0 wake state. Figure 2 shows the
transition of the ISL6506BIBZ from the S4/S5 state to the S0
state. Figure 3 shows how the ISL6506BIBZ will transition
from the S3 sleep state into S0 state. For all transitions, t4
depicts the system transition into the S0 state. Here, the ATX
supplies are enabled and begin to ramp up. At time t5, the
12V_ATX rail has exceeded the POR threshold. Three soft-
start periods after time t5, at time t6, three events occur
simultaneously. The DLA pin is forced to a high impedance
state, which allows the 12V rail to enhance the two N-
MOSFETs (Q₁ and Q₃) that connect the ATX rails to the
3.3V_DUAL and 5V_DUAL rails. The 5VDLSB pin is actively
pulled high, which will turn the P-MOSFET (Q₂) off. Finally,
the internal LDO which regulates the 3.3V_DUAL rail in sleep
states is put in standby mode.
5VSB
(1V/DIV)
5VDUAL
(1V/DIV)
3.3VDUAL
(2V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
0V
5VDLSB
(5V/DIV)
DLA
(10V/DIV)
t0 t1 t2 t3
t4 t5
t6
TIME
FIGURE 3. SOFT-START INTERVAL FOR S3 TO S0
TRANSITION FOR ISL6506BIBZ
Internal Linear Regulator Undervoltage Protection
The undervoltage protection on the internal linear regulator
is only active during sleep states and after the initial soft-start
ramp of the 3.3V linear regulator. The undervoltage trip point
is set at 25% below nominal, or 2.475V.
When an undervoltage is detected, the 3.3V linear regulator
is disabled. One soft-start interval later, the 3.3V linear
regulator is retried with a soft-start ramp. If the linear
regulator is retried 3 times and a fourth undervoltage is
detected, then the 3.3V linear regulator is disabled and can
only be reset through a POR reset.
Internal Linear Regulator Overcurrent Protection
When an overcurrent condition is detected, the gate voltage
to the internal NMOS pass element is reduced, which
causes the output voltage of the linear regulator to be
reduced. When the output voltage is reduced to the
undervoltage trip point, the undervoltage protection is
initiated and the output will shutdown.
Layout Considerations
The typical application employing an ISL6506BIBZ is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, not excessively far
from the 3.3V_DUAL island or the I/O circuitry. Ensure the
3V3AUX connection is properly sized to carry 1A without
exhibiting significant resistive losses at the load end.
Similarly, the input bias supply (5V_SB) carries a similar level
of current (for best results, ensure it is connected to its
respective source through an adequately sized trace and is
5
FN7814.0
June 8, 2011