ISL6341ACRZ-T Datasheet, PDF (5/17 Pages) Intersil Corporation – 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6341, ISL6341A, ISL6341B, ISL6341C
Electrical Specifications
Test Conditions: V_CC = 12V, T_J = 0°C to +85°C, Unless Otherwise Noted. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Upper Gate Sink Impedance
Lower Gate Source Impedance
Lower Gate Sink Impedance
PROTECTION/DISABLE
R_UG-SNKl
R_LG-SRCl
R_LG-SNKl
V_CC = 5V; I = 50mA
V_CC = 5V; I = 50mA
V_CC = 5V; I = 50mA
1.7
Ω
1.5
Ω
1.1
Ω
OCSET Current Source
Enable Threshold (COMP/EN pin)
VOS Rising Trip (PGOOD OV; +10%)
I_OCSET LGATE/OCSET = 0V
V_ENABLE
9
10
11
µA
0.683 0.700 0.717
V
0.868 0.880 0.888
V
VOS Rising Trip (PGOOD OV) Hysteresis
16
mV
VOS Falling Trip (PGOOD UV; -10%)
0.708 0.720 0.732
V
VOS Falling Trip (PGOOD UV) Hysteresis
16
mV
VOS Rising Threshold (OV; +25%)
0.980 1.000 1.020
V
VOS Falling Threshold (UV; -25%)
(Note 5)
0.580 0.600 0.620
V
VOS Threshold (OV; 50% of V_OUT)
VOS Bias Current
VOS = 0.25V
0.380 0.400 0.410
V
-1500 -250
-100
nA
PGOOD
I_PGOOD = 4mA
NOTES:
3. Limits should be considered typical and are not production tested.
4. Limits established by characterization and are not production tested.
5. The UVP is disabled on the ISL6341C; no trip point is measured.
0.10
0.18
0.30
V
Functional Pin Description
VCC (Pin 6)
This pin provides the bias supply for the ISL6341x, as well
as the lower MOSFET’s gate. An internal regulator will
supply bias as VCC rises above 5V, but the LGATE/OCSET
will still be sourced by VCC. Connect a well-decoupled 5V to
12V supply to this pin.
FB (Pin 8)
This pin is the inverting input of the internal error amplifier. Use
FB, in combination with the COMP/EN pin, to compensate the
voltage-control feedback loop of the converter. A resistor divider
from V_OUT to FB to GND is used to set the regulation voltage.
VOS (Pin 9)
This input pin monitors the regulator output for OV and UV
protection, and PGOOD (OV and UV). Connect a resistor
divider from V_OUT to VOS to GND, with the same ratio as
the FB resistor divider. It is not recommended to share one
divider for both FB and VOS; the response to a fault may not
be as quick or robust. There is a small pull-up bias current
on the pin; if the VOS pin is not connected, the OV protection
would be tripped to protect the load.
GND (Pin 5)
This pin represents the signal and power ground for the IC.
This pin is the high current connection, and should be tied to
the ground island/plane through the lowest impedance
connection available. The metal pad under the package
should also be connected to the GND plane for thermal
conductivity, but does not conduct any current.
PHASE (Pin 2)
Connect this pin to the source of the upper MOSFET, and
the drain of the lower MOSFET. It is used as the sink for the
UGATE driver, and to monitor the voltage drop across the
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry
to determine when the upper MOSFET has turned off.
UGATE (Pin 3)
Connect this pin to the gate of upper MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT (Pin 1)
This pin provides ground referenced bias voltage to the upper
MOSFET driver. A bootstrap circuit is used to create a voltage
suitable to drive an N-Channel MOSFET (equal to V_GD minus
the BOOT diode voltage drop), with respect to PHASE.
COMP/EN (Pin 7)
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/EN, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.
5
FN6538.2
December 2, 2008