ISL6206 Datasheet, PDF (5/6 Pages) Intersil Corporation – High Voltage Synchronous Rectified Buck MOSFET Driver

ISL6206
Three-state PWM Input
A unique feature of the ISL6206 and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the output drivers are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the gate driver has turned off one
MOSFET before the gate voltage of the other MOSFET is
allowed to rise.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the upper MOSFET gate voltage during UGATE
turn-off. Once the upper MOSFET gate-to-source voltage has
dropped below a threshold of 1V, the LGATE is allowed to
rise.
Bootstrap Diode and Capacitor
This driver features an internal Schottky bootstrap diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage
rating above the maximum battery voltage plus 5V. The
bootstrap capacitor can be chosen from the following
equation:
C_BOOT ≥ _∆--^Q---_V--^G--_B---^A-_O---^T-_O--^E---_T-
where Q_GATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The ∆V_BOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q_GATE, of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125µF is required.
The next larger standard value capacitance is 0.22µF. A
good quality ceramic capacitor is recommended.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125^oC. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
P = f_sw(1.5V_UQ_U + V_LQ_L) + I_DDQV_CC
where f_sw is the switching frequency of the PWM signal. V_U
and V_L represent the upper and lower gate rail voltage. Q_U
and Q_L is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The I_DDQ V_CC product is the quiescent power
of the driver and is negligible
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