ISL6206 Datasheet, PDF (4/6 Pages) Intersil Corporation – High Voltage Synchronous Rectified Buck MOSFET Driver

ISL6206
Functional Pin Description
UGATE (Pin 1)
Upper gate drive output. Connect to the gate of the high-side
N-Channel power MOSFET.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of any Intersil
multiphase controllers.
GND (Pin 4)
Ground pin. All signals are referenced to this node.
LGATE (Pin 5)
Lower gate drive output. Connect to the gate of the low-side
N-Channel power MOSFET.
VCC (Pin 6)
Connect this pin to a +5V bias supply. Place a high quality
bypass capacitor from this pin to GND.
NC (Pin 7)
No connection. Leave this pin floating.
Timing Diagram
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. This pin provides a return path
for the upper gate driver.
Description
Operation
The ISL6206 dual MOSFET driver controls both high-side and
low-side N-Channel FETs from one externally provided PWM
signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t_PDLLGATE], the lower gate begins to fall. Typical fall
times [t_FLGATE] are provided in the Electrical Specifications
section. Adaptive shoot-through circuitry monitors the
LGATE voltage and determines the upper gate delay time
[t_PDHUGATE] based on how quickly the LGATE voltage
drops below 1V. This prevents both the lower and upper
MOSFETs from conducting simultaneously or shoot-
through. Once this delay period is complete the upper gate
drive begins to rise [t_RUGATE] and the upper MOSFET turns
on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t_PDLUGATE] is encountered before the
upper gate begins to fall [t_FUGATE]. Again, the adaptive
shoot-through circuitry determines the lower gate delay time,
t_PDHLGATE. The upper MOSFET gate voltage is monitored
and the lower gate is allowed to rise after the upper MOSFET
gate-to-source voltage drops below 1V. The lower gate then
rises [t_RLGATE], turning on the lower MOSFET.
PWM
t_PDHUGATE
UGATE
LGATE
t_RUGATE
t_PDLUGATE
t_FUGATE
t_PDLLGATE
t_FLGATE
t_PDHLGATE
t_RLGATE
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