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ISL54500 Datasheet, PDF (5/13 Pages) Intersil Corporation – +1.8V to +5.5V, 5OHM, Single SPDT Analog Switch
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ISL54500
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V
(Note 10), Unless Otherwise Specified. Boldface limits apply over the operating
temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+
TEMP
MIN
MAX
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
25
-
0.02
-
µA
Full
-
0.11
-
µA
Full
-
-
0.5
V
Full
1.4
-
-
V
Full
-0.1
0.049
0.1
µA
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 10),
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Full
0
-
V+
V
ON-Resistance, rON
V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0V 25
-
11.9
12.8
Ω
to V+, (Note 14, See Figure 5)
Full
-
-
13.8
Ω
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω,
25
-
70
-
ns
CL = 35pF (See Figure 1)
Full
-
130
-
ns
Turn-OFF Time, tOFF
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω,
25
-
52
-
ns
CL = 35pF (See Figure 1)
Full
-
100
-
ns
Break-Before-Make Time Delay, V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, Full
-
42
-
ns
tD
CL = 35pF (See Figure 3)
Charge Injection, Q
VG = 0, RG = 0Ω, CL = 1.0nF (See Figure 2) 25
-
5.8
-
pC
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
-
0.4
V
Input Voltage High, VINH
Full
1
-
-
V
NOTES:
10. VIN = input voltage to perform proper function.
11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
13. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
14. Limits established by characterization and are not production tested.
5
FN6549.2
November 9, 2009
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