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ISL54207 Datasheet, PDF (5/14 Pages) Intersil Corporation – Low Voltage, Dual SPDT, USB/CVBS/ Audio Switches, with Negative Signal Capability
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ISL54207
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VBUSH = 3.8V, VBUSL = 3.2V,
VCTRLH = 1.4V, VCTRLL = 0.5V, (Notes 4, 6), unless otherwise specified.
(Continued)
PARAMETER
TEST CONDITIONS
TEMP (NOTE 5)
(NOTE 5)
(°C)
MIN
TYP
MAX UNITS
CTRL Voltage High, VCTRLH
VDD = 2.7V to 3.6V
Full
1.4
-
-
V
Input Current, IBUSL, ICTRLL
VDD = 3.6V, VBUS = 0V or float, CTRL = 0V or float
Full
-50
20
50
nA
Input Current, IBUSH
VDD = 3.6V, VBUS = 5.25V, CTRL = 0V or float
Full
-2
1.1
2
μA
Input Current, ICTRLH
VDD = 3.6V, VBUS = 0V or float, CTRL = 3.6V
Full
-2
1.1
-2
μA
VBUS Pull-Down Resistor, RVBUS VDD = 3.6V, VBUS = 5.25V, CTRL = 0V or float
Full
-
4
-
MΩ
CTRL Pull-Down Resistor, RCTRL VDD = 3.6V, VBUS = 0V or float, CTRL = 3.6V
Full
-
4
-
MΩ
NOTES:
4. VLOGIC = Input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2 or between NO1 and NO2.
Test Circuits and Waveforms
VBUSH
LOGIC
INPUT
VBUSL
50%
tOFF
tr < 20ns
tf < 20ns
SWITCH
INPUT
VINPUT
VOUT
90%
90%
SWITCH
OUTPUT
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
VDD
C
VINPUT
SWITCH
INPUT
CTRL
NO or NC
VBUS
COMx
VBUS
GND
VOUT
RL
CL
50Ω 10pF
Repeat test for all switches. CL includes fixture and stray
capacitance.
VOUT
=
V (INPUT)
-----------R-----L-----------
RL + r(ON)
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
FIGURE 1B. TEST CIRCUIT
5
FN6403.0
December 5, 2006
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