ISL45041_1012 Datasheet, PDF (5/7 Pages) Intersil Corporation – TFT-LCD I2C Programmable VCOM Calibrator

ISL45041
Application Information
This device provides the ability to reduce the flicker of an LCD
panel by adjustment of the V_COM voltage during production
test and alignment. A 128-step resolution is provided under
digital control, which adjusts the sink current of the output.
The output is connected to an external voltage divider, so that
the device will have the capability to reduce the voltage on the
output by increasing the output sink current.
AVDD
AVDD
ISL45041
SET
OUT
R₁
-
+
R_SET
R₂
I_OUT
FIGURE 1. OUTPUT CONNECTION CIRCUIT EXAMPLE
The adjustment of the output is provided by the 2-wire I²C
serial interface.
Expected Output Voltage
The ISL45041 provides an output sink current, which lowers
the voltage on the external voltage divider (V_COM output
voltage). Equation 1 and Equation 2 can be used to calculate
the output current (I_OUT) and output voltage (V_OUT) values.
The setting is the register value +1 with a value between 1
and 128.
I_OUT
=
S_-----e_----t_--t_--i_--n_----g_-
128
x
------^A----^V-----^D----^D-------
20 ( R_{S E T} )
(EQ. 1)
V_OUT
=
⎛
⎜
⎝
-_R----₁--^R---+--²--_R-----₂-_{⎠⎟⎞}
⎛
AV_D
D
⎜1
⎝
–
S_-----e_----t_--t_--i_--n_----g_-
128
x
-₂---₀----₍--_R-^R----_S1----_E---_T----_{)⎠⎟⎞}
(EQ. 2)
Table 1 gives the calculated value of V_OUT using the resistor
values of: R_SET = 24.9kΩ, R₁ = 200kΩ, R₂ = 243kΩ, and
AV_DD = 10V.
TABLE 1.
SETTING VALUE
1
V_OUT
5.486
10
5.313
20
5.141
30
4.969
40
4.797
50
4.625
60
4.453
70
4.281
80
4.109
90
3.936
100
3.764
110
3.592
128
3.282
R_SET Resistor
The external R_SET resistor sets the full-scale sink current, I_SET
maximum, that determines the lowest voltage of the external
voltage divider R₁ and R₂ (Figure 1). The voltage difference
between the OUT pin and SET pin (Figure 2), which are also
the drain and source of the output transistor, must be greater
than 1.75V. This will keep the output transistor in its saturation
region to maintain linear operation over the full range of register
values. Expected current settings and 7-bit accuracy occurs
when the output MOS transistor is operating in the saturation
region. Figure 2 shows the internal connection for the output
MOS transistor. The value of the AV_DD supply sets the voltage
at the source of the output transistor. This voltage is equal to
(Setting/128) x (AV_DD/20). The I_SET current is therefore equal
to (Setting/128) x (AV_DD/20 x R_SET). The drain voltage is
calculated using Equation 2. The values of R₁ and R₂
(Equation 2) should be determined using I_OUT maximum
(setting equal to 128) so the minimum value of V_OUT is greater
than 1.75V + AV_DD/20.
S-----E----T-----T----I--N-----G--- _x ^{A-----V-----D----D---}
128
20
OUT PIN
AV_DD = 15V
R1
AVDD
VSAT
R2
0.5V
R_SET
SET PIN
FIGURE 2. OUTPUT CONNECTION CIRCUIT EXAMPLE
Ramp-Up of the VDD Power Supply
The ramp-up from 10% V_DD to 90% V_DD level must be
achieved in 10ms or less to ensure that the EEPROM and
power-on-reset circuits are synchronized and the correct
value is read from the EEPROM Memory.
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 3. When applying power, VDD should be applied
before or at the same time as AVDD. The minimum time for
t_VS is 0µs. When removing power, the sequence of VDD and
AVDD is not important.
V_DD
A_VDD
t_VS
FIGURE 3. POWER SUPPLY SEQUENCE
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
5
FN6189.4
December 17, 2010