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ISL45041_1012 Datasheet, PDF (4/7 Pages) Intersil Corporation – TFT-LCD I2C Programmable VCOM Calibrator
ISL45041
Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ; (See Figure 1) Unless
Otherwise Specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, 0°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
MAX
TYP (Note 6) UNITS
SDA, SCL Input Logic High
SDA, SCL Input Logic Low
I2CVIH
I2CVIL
0.7*VDD
V
0.55 V
SDA, SCL Hysteresis
(Note 9)
260
mV
SDA Output Logic High
SDA Output Logic Low
WP Input Logic High
WP Input Logic Low
WP Hysteresis
WP Input Current
I2C Timing
VOHS
VOLS
VIH
VIL
ILWPN
@ 3mA
(Note 9)
VDD - 0.4
0.7*VDD
0.20
V
0.4
V
V
0.3*VDD V
0.14VDD
V
35
µA
SCL Clock Frequency
I2C Clock High Time
I2C Clock Low Time
I2C Spike Rejection Filter Pulse Width
I2C Data Set Up Time
I2C Data Hold Time
I2C SDA, SCL Input Rise Time
I2C SDA, SCL Input Fall Time
I2C Bus Free Time Between Stop and Start
I2C Repeated Start Condition Set-up
I2C Repeated Start Condition Hold
I2C Stop Condition Set-up
I2C Bus Capacitive Load
fSCL
tSCH
tSCL
tDSP
tSDS
tSDH
tICR
tICF
tBUF
tSTS
tSTH
tSPS
Cb
Dependent on Load (Note 10)
(Note 10)
0
400 kHz
0.6
µs
1.3
µs
0
50
ns
100
ns
900
ns
20 + 0.1*Cb 1000 ns
20 + 0.1*Cb 300 ns
200
µs
0.6
µs
0.6
µs
0.6
µs
400 pF
SDA Pin Capacitance
CSDA
10
pF
SCL Pin Capacitance
CS
10
pF
EEPROM Write Cycle Time
tW
100 ms
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. IDD current may increase to 2mA for 45ms or less during each EEPROM programming operation.
8. IAVDD current may increase to 1mA for 30ms or less during each EEPROM programming operation.
9. Simulated and Determined via Design and NOT Directly Tested.
10. Simulated and Designed According to I2C Specifications.
11. A typical Current of 20μA is Calculated using AVDD = 10V and RSET = 24.9kΩ. Reference “RSET Resistor” in Figure 2.
12. Minimum value of RSET resistor guaranteed when: AVDD = 15V, VDD = 3.0V and when voltage on the VOUT pin is greater than 2.5V. Reference
Equation 2 on page 5 with Setting = 128.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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4
FN6189.4
December 17, 2010