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ISL43681_06 Datasheet, PDF (5/17 Pages) Intersil Corporation – Low-Voltage, Single and Dual Supply, 8 to 1 Multiplexer and Differential 4 to 1 Multiplexer
◁
ISL43681, ISL43741
Electrical Specifications +12V Supply
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 3),
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP (NOTE 4)
(°C)
MIN
(NOTE 4)
TYP
MAX UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V
(See Figure 6)
Full
0
25
-
Full
-
-
V+
V
37
45
Ω
-
55
Ω
RON Matching Between Channels, V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V (Note 5) 25
-
1.2
2
Ω
∆RON
Full
-
-
2
Ω
RON Flatness, RFLAT(ON)
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V
25
-
5
7
Ω
(Note 6)
Full
-
-
7
Ω
NO or NC OFF Leakage Current, V+ = 13.2V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V
25
-0.1
0.002
0.1
nA
INO(OFF) or INC(OFF)
(Note 7)
Full
-2.5
-
2.5
nA
COM OFF Leakage Current,
ICOM(OFF)
V+ = 13.2V, VCOM = 12V, 1V, VNO or VNC = 1V, 12V
25
-0.1
0.002
0.1
nA
(Note 7)
Full
-2.5
-
2.5
nA
COM ON Leakage Current,
ICOM(ON)
V+ = 13.2V, VCOM = 1V, 12V, VNO or VNC = 1V, 12V,
25
-0.1
0.002
0.1
nA
or floating (Note 7)
Full
-2.5
-
2.5
nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, VINH, VADDH
Input Voltage Low, VINL, VADDL
Input Current, IADDH, IADDL, IENH, V+ = 13.2V, VINH, VADD = 0V or V+
IENL
Input Current, IENH, ILEH
V+ = 13.2V, VINH, VADD = 0V or V+
Input Current, IENL, ILEL
V+ = 13.2V, VINH, VADD = 0V or V+
DYNAMIC CHARACTERISTICS
Full
3.7
3.3
Full
-
2.7
Full
-0.5
-
Full
-1.5
-
Full
-4
-
-
V
0.8
V
0.5
µA
1.5
µA
4
µA
Enable Turn-ON Time, tON
V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF, 25
-
VIN = 0 to 4 (See Figure 1)
Full
-
24
40
ns
-
45
ns
Enable Turn-OFF Time, tOFF
V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF, 25
-
VIN = 0 to 4 (See Figure 1)
Full
-
15
30
ns
-
35
ns
Address Transition Time, tTRANS V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF, 25
-
VIN = 0 to 4 (See Figure 1)
Full
-
27
50
ns
-
55
ns
Break-Before-Make Time Delay, tD V+ = 13.2V, RL = 300Ω, CL = 35pF, VNO or VNC = 10V, Full
2
5
VIN = 0 to 4 (See Figure 3)
Latch Setup Time, tS
(See Figure 4)
25
25
-
Full
35
-
-
ns
-
ns
-
ns
Latch Hold Time, tH
(See Figure 4)
25
0
-
-
ns
Full
0
-
-
ns
Latch Pulse Width, tWPW
(See Figure 4)
25
15
-
Full
25
-
-
ns
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2)
25
-
2.7
5
pC
5
FN6053.3
March 13, 2006
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