ISL22317_14 Datasheet, PDF (5/15 Pages) Intersil Corporation – Low Noise, Low Power, I2C™ Bus, 128 Taps

ISL22317
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 22) (Note 7) (Note 22)
t_D
Power-up Delay
VR_CegCisatbeor vreecVapllocro, _{mtopDleCtePd,InaintidalIV2CaluIneterface}
1
in standby state
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
EEPROM Retention
Temperature T ≤ +55°C
50
Temperature T ≤ +125°C
15
t_WC
Non-volatile Write Cycle Time
(Note 21)
12
20
SERIAL INTERFACE SPECS
V_IL
A1, A0, SDA, and SCL Input Buffer
LOW Voltage
0.3*V_CC
V_IH
A1, A0, SDA, and SCL Input Buffer
HIGH Voltage
0.7*V_CC
Hysteresis SDA and SCL Input Buffer Hysteresis
(Note 19)
0.05*V_CC
V_OL
SDA Output Buffer LOW Voltage,
(Note 19) Sinking 4mA
0
0.4
Cpin A1, A0, SDA, and SCL Pin
10
(Note 19) Capacitance
f_SCL
SCL Frequency
400
t_sp
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
50
and SCL Inputs
suppressed
t_AA
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V_CC, until
900
Valid
SDA exits the 30% to 70% of V_CC window
t_BUF
Time the Bus must be Free Before the SDA crossing 70% of V_CC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of V_CC
during the following START condition
1300
t_LOW
t_HIGH
t_SU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
t_HD:STA START Condition Hold Time
t_SU:DAT Input Data Setup Time
t_HD:DAT Input Data Hold Time
Measured at the 30% of V_CC crossing
Measured at the 70% of V_CC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of V_CC
From SDA falling edge crossing 30% of V_CC
to SCL falling edge crossing 70% of V_CC
From SDA exiting the 30% to 70% of V_CC
window, to SCL rising edge crossing 30% of
V_CC
From SCL falling edge crossing 70% of V_CC
to SDA entering the 30% to 70% of V_CC
window
1300
600
600
600
100
0
t_SU:STO
t_HD:STO
t_DH
STOP Condition Setup Time
From SCL rising edge crossing 70% of V_CC,
to SDA rising edge crossing 30% of V_CC
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;
or Volatile Only Write
both crossing 70% of V_CC
Output Data Hold Time
From SCL falling edge crossing 30% of V_CC,
until SDA enters the 30% to 70% of V_CC
window
600
1300
0
UNIT
ms
Cycles
Years
Years
ms
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
FN6912.1
April 15, 2010