ISL12024 Datasheet, PDF (5/25 Pages) Intersil Corporation – Real-Time Clock/Calendar with Embedded Unique ID

ISL12024
AC Electrical Specifications (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 12) TYP (Note 12) UNITS NOTES
Cpin SDA and SCL Pin Capacitance
10
pF
t_WC Non-Volatile Write Cycle Time
t_R
SDA and SCL Rise Time
From 30% to 70% of V_DD (Note 11)
12
20
ms
20 +
0.1 x Cb
300
ns
11
t_F
SDA and SCL Fall Time
From 70% to 30% of V_DD (Note 11)
20 +
0.1 x Cb
300
ns
11
Cb Capacitive Loading of SDA or Total on-chip and off-chip. (Note 11)
SCL
10
400
pF
11
R_PU SDA and SCL Bus Pull-up
Maximum is determined by t_R and t_F.
1
Resistor Off-chip
For Cb = 400pF, max is about 2kΩ~2.5kΩ.
For Cb = 40pF, max is about 15kΩ~20kΩ
kΩ
11
NOTES:
3. IRQ/F_OUT Inactive.
4. V_IL = V_DD x 0.1, V_IH = V_DD x 0.9, f_SCL = 400kHz
5. V_DD > V_BAT +V_BATHYS
6. Bit BSW = 0 (Standard Mode), ATR = 00h, V_BAT ≥1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the V_{DD SR-} specification must be followed.
9. Parameter is not 100% tested.
10. t_WC is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end
of Write sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
11. These are I²C specific parameters and are not directly tested, however they are used during device testing to validate device
specification.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Timing Diagrams
Bus Timing
SCL
t_SU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
Write Cycle Timing
t_F
t_HIGH
t_SU:DAT
t_HD:STA
t_LOW
t_R
t_HD:DAT
t_AA
t_DH
t_HD:STO
t_SU:STO
t_BUF
SCL
SDA
8TH BIT OF LAST BYTE
ACK
5
t_WC
STOP
CONDITION
START
CONDITION
FN6370.3
August 18, 2008