ISL12024 Datasheet, PDF (22/25 Pages) Intersil Corporation – Real-Time Clock/Calendar with Embedded Unique ID

ISL12024
2.7V TO 5.5V
V_DD V_BAT
V_SS
SUPER CAP
FIGURE 24. SUPER CAPACITOR CHARGING CIRCUIT
Alarm Operation Examples
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm0 set with single interrupt (IM = “0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm0 registers as follows:
BIT
ALARM0
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled
MNA0 1 0 1 1 0 0 0 0 B0h Minutes set to 30,
enabled
HRA0 1 0 0 1 0 0 0 1 91h Hours set to 11,
enabled
DTA0
1 0 0 0 0 0 0 1 81h Date set to 1,
enabled
MOA0 1 0 0 0 0 0 0 1 81h Month set to 1,
enabled
DWA0 0 0 0 0 0 0 0 0 00h Day of week
disabled
B. Also, the AL0E bit must be set as follows:
BIT
CONTROL
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
INT
0 0 1 0 0 0 0 0 x0h Enable Alarm
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1” and also bringing the IRQ/F_OUT output
low.
EXAMPLE 2
Pulsed interrupt once per minute (IM = “1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm0 registers as follows:
B. Set the Interrupt register as follows:
BIT
ALARM0
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
SCA0
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
enabled
MNA0 0 0 0 0 0 0 0 0 00h Minutes disabled
HRA0 0 0 0 0 0 0 0 0 00h Hours disabled
DTA0 0 0 0 0 0 0 0 0 00h Date disabled
MOA0 0 0 0 0 0 0 0 0 00h Month disabled
DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled
BIT
CONTROL
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
INT 1 0 1 0 0 0 0 0 x0h Enable Alarm and Int
Mode
Once the registers are set, the following waveform will be
seen at IRQ/F_OUT:
RTC AND ALARM REGISTERS ARE BOTH 30s
60s
Note that the status register AL0 bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
I²C Communications During Battery Backup
Operation in Battery Backup Mode is affected by the BSW
and SBIB bits as described earlier. These bits allow flexible
operation of the serial bus and EEPROM in Battery Backup
Mode, but certain operational details need to be clear before
utilizing the different modes. Table 8 describes four different
modes possible with using the BSW and SBIB bits, and how
they affect the serial interface and battery backup operation.
• Mode A - In this mode, selection bits indicate a Standard
Mode switchover combined with I²C operation in Battery
Backup Mode. When the V_DD voltage drops below the
lower of V_TRIP or V_BAT, then the device will enter Battery
Backup Mode. If the microcontroller and bus pull-ups are
also powered by the battery, then the ISL12024 can
communicate in Battery Backup Mode.
• Mode B - In this mode selection, bits indicate Legacy
Mode switchover combined with I²C operation in Battery
Backup Mode. When the V_DD voltage drops below V_BAT,
the device will enter Battery Backup Mode. If the
microcontroller and bus pull-ups are also powered by the
battery, then the ISL12024 can communicate in Battery
Backup Mode. This mode places the ISL12024 device in
the same operating mode as the X1226 legacy device.
• Mode C - This mode combines Standard Mode battery
switchover with no I²C operation in Battery Backup Mode.
When the V_DD voltage drops below the lower of V_TRIP or
22
FN6370.3
August 18, 2008