DG444 Datasheet, PDF (5/10 Pages) Intersil Corporation – Monolithic, Quad SPST, CMOS Analog Switches

DG444, DG445
Test Circuits and Waveforms
V_O is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing
edge of the output waveform.
3V
LOGIC
INPUT
0V
SWITCH
INPUT
V_S
SWITCH
OUTPUT _0V
50%
t_OFF
V_O
80%
t_r < 20ns
t_f < 20ns
80%
t_ON
NOTE: Logic input waveform is inverted for switches that have
the opposite logic sense.
V_L
V+
SWITCH
INPUT
S₁
IN₁
D₁
V_O
LOGIC
INPUT
3V
GND
R_L
C_L
V-
Repeat test for Channels 2, 3 and 4.
For load conditions, see Specifications. C_L includes fixture and
stray capacitance.
V_O = V_S -_R----_L-----+----_r-^R--_D---^L-_S----₍--_O----_N-----₎
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
FIGURE 1B. TEST CIRCUIT
SWITCH
OUTPUT
∆V_O
V_L
R_G
V+
D₁
IN_X
(DG444)
OFF
ON
OFF
V_G
IN_X
(DG445) OFF
ON
Q = ∆V_O x C_L
OFF
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V-
V_IN = 3V
GND
FIGURE 2B. TEST CIRCUIT
V_O
C_L
V+ ^+15V
C
SIGNAL
GENERATOR 10dBm
V_S
V_D
50Ω
+15V
C V+
SIGNAL
GENERATOR 10dBm
V_S
0V, 2.4V
IN₁
IN₂
0V, 2.4V
ANALYZER
R_L
V_D
GND ^V-
NC
C
-15V
FIGURE 3. CROSSTALK TEST CIRCUIT
IN_X
0V, 2.4V
ANALYZER
R_L
V_D
C
GND ^V-
-15V
FIGURE 4. OFF ISOLATION TEST CIRCUIT
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