CDP1821C Datasheet, PDF (5/7 Pages) Intersil Corporation – High-Reliability CMOS 1024-Word x 1-Bit Static RAM

CDP1821C/3
Write Cycle Dynamic Electrical Specifications t_R, t_F = 10ns, C_L = 50pF
PARAMETER
SYMBOL
V_DD
(V)
-55^oC, +25^oC
MIN
MAX
+125^oC
MIN
MAX
Write Cycle Time
t_WC
5
300
-
420
-
Address Setup Time (Note 1)
t_AS
5
60
-
84
-
Address Hold Time (Note1)
t_AH
5
130
-
180
-
Input Data Setup Time (Note 1)
t_DS
5
90
-
125
-
Input Data Hold Time (Note 1)
t_DH
5
60
-
84
-
Read/Write Pulse Width Low (Note 1)
t_WL
5
110
-
155
-
NOTE:
1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
UNITS
ns
ns
ns
ns
ns
ns
CS
(NOTE 1)
(NOTE 2)
A0 - A9
R/W
(NOTE 3)
t_AS
DI
(NOTE 3)
t_WC
t_WL
t_DS
t_AH
t_DH
(NOTE 3)
NOTES:
1. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device.
2. Chip-Select (CS) permitted to change from low to high level or remain low.
3. Don’t care.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
6-9