CDP1821C Datasheet, PDF (1/7 Pages) Intersil Corporation – High-Reliability CMOS 1024-Word x 1-Bit Static RAM

CDP1821C/3
March 1997
High-Reliability CMOS
1024-Word x 1-Bit Static RAM
Features
Description
• Static CMOS Silicon-On-Sapphire Circuitry CD4000-
Series Compatible
• Compatible with CDP1800-Series Microprocessors at
Maximum Speed
• Fast Access Time. . . . . . . . . . . 100ns Typ. at V_DD = 5V
• Single Voltage Supply
• No Precharge or External Clocks Required
• Low Quiescent and Operating Power
• Separate Data Inputs and Outputs
• High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of V_DD
• Memory Retention for Standby Battery Voltage Down
to 2V at +25^oC
• Latch-Up-Free Transient-Radiation Tolerance
The CDP1821C/3 is a 1024-word x 1-bit CMOS silicon-on-sap-
phire (SOS), fully static, random-access memory designed for
use in CDP1800 microprocessor systems. This device has a
recommended operating voltage range of 4V to 6.5V.
The output state of the CDP1821C/3 is a function of the
input address and chip-select states only. Valid data will
appear at the output in one access time following the latest
address change to a selected chip. After valid data appears,
the address may be changed immediately. It is not neces-
sary to clock the chip-select input or any other input terminal
for fully static operation; therefore the chip-select input may
be used as an additional address input. When the device is
in an unselected state (CS = 1), the internal write circuitry
and output sense amplifier are disabled. This feature allows
the three-state data outputs from many arrays to be OR-tied
to a common bus for easy memory expansion.
Ordering Information
PACKAGE
SBDIP
TEMP. RANGE
-55^oC to +125^oC
PART
NUMBER PKG. NO.
CDP1821CD3 D16.3
Pinout
CDP1821C/3
(SBDIP)
TOP VIEW
CS 1
A0 2
A1 3
A2 4
A3 5
A4 6
DO 7
V_SS 8
16 V_DD
15 DI
14 RD/WR
13 A9
12 A8
11 A7
10 A6
9 A5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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