CD4555BMS Datasheet, PDF (5/11 Pages) Intersil Corporation – CMOS Dual Binary to 1 of 4 Decoder/Demultiplexers

Specifications CD4555BMS, CD4556BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
PART NUMBER CD4555BMS & CD4556BMS
Static Burn-In 1 4 - 7, 9 - 12
1 - 3, 8, 13 - 15
16
Note 1
Static Burn-In 2
Note 1
4 - 7, 9 - 12
8
1 - 3, 13 - 16
Dynamic Burn-
-
In Note 1
1, 8, 15
16
4 - 7, 9 - 12
2, 14
3, 13
Irradiation
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagrams
2(14)
A
*
3(13)
B
*
1(15)
E
*
*ALL INPUTS PROTECTED BY CMOS
PROTECTION NETWORK
4(12)
Q0
5(11)
Q1
6(10)
Q2
7(9)
Q3
VDD
2(14)
A
*
3(13)
B
*
1(15)
E
*
*ALL INPUTS PROTECTED BY CMOS
PROTECTION NETWORK
4(12)
Q0
5(11)
Q1
6(10)
Q2
7(9)
Q3
VDD
VSS
FIGURE 1. CD455RBMS LOGIC DIAGRAM (1 OF 2 IDENTICAL
CIRCUITS)
VSS
FIGURE 2. CD4556BMS LOGIC DIAGRAM (1 OF 2 IDENTICAL
CIRCUITS)
7-1253