CD4019BMS Datasheet, PDF (5/9 Pages) Intersil Corporation – CMOS Quad AND/OR Select Gate

Specifications CD4019BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
Static Burn-In 1
Note 1
OPEN
10 -13
GROUND
1 - 9, 14, 15
VDD
16
9V ± -0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 2
Note 1
10 -13
8
1 - 7, 9, 14 - 16
Dynamic Burn-
-
In Note 1
8
16
10 - 13
-
1 - 7, 9, 14, 15
Irradiation
Note 2
10 -13
8
1 - 7, 9, 14 - 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
*Ka 9
VDD = 16
VSS - 8
*Kb 14
*A4 15
*B4 1
VDD *A3 2
*B3 3
*A2 4
VSS *B2 5
*INPUTS PROTECTED
BY CMOS PROTECTION
*A1
6
NETWORK
*B1 7
TO 3 MORE
SIMILAR
CIRCUITS
13 D4
12 _D3
11 _D2
10
D1
TRUTH TABLE
Ka
Kb
An
Bn
Dn
1
0
1
X
1
1
0
0
X
0
0
1
X
1
1
0
1
X
0
0
0
0
X
X
0
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
X = Don’t Care Case
FIGURE 1. CD4019BMS LOGIC DIAGRAM
7-311