CD4019BMS Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS Quad AND/OR Select Gate

CD4019BMS
November 1994
CMOS Quad AND/OR Select Gate
Features
Pinout
• High Voltage Type (20V Rating)
• Medium Speed Operation tPHL = tPLH = 60ns (typ.) at
CL = 50pF, VDD = 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
• Maximum Input Current of 1µa at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25^oC
B4 1
A3 2
B3 3
A2 4
B2 5
A1 6
B1 7
VSS 8
CD4019BMS
TOP VIEW
16 VDD
15 A4
14 Kb
13 D4 = A4 Ka + B4 Kb
12 D3 = A3 Ka + B3 Kb
11 D2 = A2 Ka + B2 Kb
10 D1 = A1 Ka + B1 Kb
9 Ka
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Applications
Functional Diagram
Ka Kb
9 14
VDD
16
• And/Or Select Gating
• Shift-Right/Shift-Left Registers
• True/Complement Selection
• AND/OR/Exclusive-OR Selection
Description
CD4019BMS types consist of four AND/OR select gate con-
figurations, each consisting of two 2-input AND gates driving
a single 2-input OR gate. Selection is accomplished by con-
trol bits Ka and Kb. In addition to selection of either channel
A or channel B information, the control bits can be applied
simultaneously to accomplish the logical A + B function.
15
A4
B4 ¹
A3 ²
B3 ³
A2 ⁴
B2 ⁵
6
A1
7
B1
13
D4
12 _D3
D4 = (A4 Ka) + (B4 Kb) ^{11 D2}
10 _D1
8
VSS
The CD4019BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP H4T
Frit Seal DIP
H1E
Ceramic Flatpack H3X
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-307
File Number 3299