HSP50214B_07 Datasheet, PDF(42/62 Page) Intersil Corporation

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HSP50214B_07 Datasheet, PDF (42/62 Pages) Intersil Corporation – Programmable Downconverter

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HSP50214B

The PDC begins to fill the buffer each time an interval

number of samples have passed. The number of sample

sets the PDC writes into the buffer and is programmed into

bits 3-0 of Control Word 21. The number of samples stored

is the programmed value and may be from 1 to 8 sample

sets. A sample set consists of I, Q, |r|, Ï and Æ.

In snap shot operations, the buffer is read the same as for

FIFO operations. Figures 37 and 39 describe the Design

Blocks and Timing required to output data on AOUT(7:0) and

BOUT(7:0). Table 17 summarizes the selectable output

signals. The method for reading data through the

Microprocessor Section in snap shot mode is identical to the

method described in the FIFO mode subsection and the

Microprocessor Read Section.

Avoiding Timing Pitfalls When Using the Buffer

RAM Output Port

In snapshot mode, the whole buffer is written whenever the

interval counter has timed-out. After time-out, old data can

be written over. Thus, the data contained within the buffer

must be retrieved before time-out to avoid data loss.

It may be desirable to disable the INTRRPT into the

controlling microprocessor during read cycles to avoid the

generating extra interrupts. Figure 44 details how the WRITE

address can trigger extra interrupts. Care must be taken to

either read sufficient data out of memory or RESET the

addressing to ensure that a complete set of data is the cause

of the interrupt.

INTRRP

TIME

A COMPLETE SET OF 3 DATA SAMPLES IS IN MEMORY AT INTRRP

A: NORMAL READ/WRITE SEQUENCE

INTRRP

INTRRP INTRRP

TIME

THE THIRD INTERRUPT HAS ONLY 1 NEW DATA ENTRY

(INSTEAD OF 3) AT INTRRP

B: FALSE TRIGGERED INTERRUPT READ/WRITE SEQUENCE

FIGURE 44. AVOIDING FALSE INTRRP ASSERTIONS

Microprocessor Write Section

The Microprocessor Write Section uses an indirect addressing

scheme where a 32-bit data word is first loaded in a four 8-bit

byte master registers using four writes via C(7:0). The desired

destination register address is then written to another address

using C(7:0). Writing this address triggers a circuit that

generates a pulse, synchronous to clock, that loads the

Destination Register. The sync circuits and data words are

synchronized to different clocks, CLKIN or PROCCLK,

depending on the Destination Registers.

A(2:0) determines the destination for the data on bus, C(7:0).

Table 19 shows the address map for microprocessor

interface. Figure 45 shows the Control Register loading

sequence. The data in C(7:0) and address map in A(2:0) is

loaded into the PDC on the rising edge of WR and is latched

into the Master Register on the rising edge of WR and A(2:0)

= 100. Four clocks must pass before loading the next Control

Word to guarantee that the data has been transferred.

Some registers can be loaded (i.e., transferred from the

Master Register to a Configuration Register or from a Holding

example, to load the AGC Gain, the value of the AGC gain is

first loaded into the Holding Registers, then a transfer is

initiated by SYNCIN2 if Control Word 8, Bit 29 = 1. This allows

the AGC gain to be loaded by detecting a system event, such

as a start of a new burst. Bit 20 of Control Word 0 has the

same effect on the Carrier NCO center frequency for assertion

of SYNCIN1, except it transfers from a dedicated holding

TABLE 19. DEFINITION OF ADDRESS MAP

A2-0

0 Holding Register 0. Transfers to bits 7-0 of the 32-bit

Destination Register. Bit 0 is the LSB of the 32-bit register.

1 Holding Register 1. Transfers to bits 15-8 of a 32-bit

Destination Register.

2 Holding Register 2. Transfers to bits 23-16 of a 32-bit

Destination Register.

3 Holding Register 3. Transfers to bits 31-24 of a 32-bit

Destination Register. Bit 31 is the MSB of the 32-bit

4 This is the Destination Address Register. On the fourth CLK

following a write to this register, the contents of the Holding

Registers are transferred to the Destination Register. All 8

bits written to this register are decoded into the Destination

map is given in the tables in the Control Word Section.

5 Selects data source for reading. See Microprocessor Read

Section.

Suppose a (0018D038)H needs to be loaded into Control Word

0, then Table 20 details the steps to be taken.

FN4450.4

May 1, 2007

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