HSP50214B_07 Datasheet, PDF (10/62 Pages) Intersil Corporation – Programmable Downconverter

HSP50214B
See Figures 4 to 7 for an interpolated input example,
detailing the associated spectral results.
Interpolation Example:
The specifications for the interpolated input example are:
CLKIN = 40MHz
Input Sample Rate = 5MSPS
PROCCLK = 28MHz
Interpolate by 8, Decimate by 10
Desired 85dB dynamic range output bandwidth = 500kHz
Input Level Detector
The Input Level Detector Section measures the average
magnitude error at the PDC input for the microprocessor by
comparing the input level against a programmable
threshold and then integrating the result. It is intended to
provide a gain error for use in an AGC loop with either the
RF/IF or A/D converter stages (see Figure 8). The AGC
loop includes Input Level Detector, the microprocessor and
an external gain control amplifier (or attenuator). The input
samples are rectified and added to a threshold
programmed via the microprocessor interface, as shown in
Figure 9. The bit weighting of the data path through the
input threshold detector is shown in Figure 10. The
threshold is a signed number, so it should be set to the
inverse of the desired input level. The threshold can be set
to zero if the average input level is desired instead of the
error. The sum of the threshold and the absolute value of
the input is accumulated in a 32-bit accumulator. The
accumulator can handle up to 2¹⁸ samples without
overflow. The integration time is controlled by an 18-bit
counter. The integration counter preload (ICPrel) is
programmed via the microprocessor interface through
Control Word 1. Only the upper 16-bits are programmable.
The 2 LSBs are always zero. Control Word 1, Bits 29-14
are programmed to:
ICPrel = (N) ⁄ 4 + 1
(EQ. 1)
where N is the desired integration period, defined as the
number of input samples to be integrated. N must be a
multiple of 4: [0, 4, 8, 12, 16 .... , 2¹⁸].
IN(13:0)
INPUT
FORMAT †
GAINADJ(2:0)
INPUT LEVEL DETECTOR †
STATUS (0) †
LEVEL
DETECT
INPUT_THRESH †
INTG_MODE †
INTG_INTEVAL †
14
15
14
15
18
18
NCO † †
4
EN
DELAY 3
LIMIT
3
∑
BYPASS †
ENI
INTERP †
4
DELAY 3
CONTROL WORD 0
CONTROL WORD 1
CLKIN
CONTROL
LOGIC
INPUT_MODE †
INPUT_FMT †
INPUT_THRESH †
INTG_MODE †
INTG_INTEVAL †
† Controlled via microprocessor interface.
†† See NCO Section for more details.
FIGURE 3. BLOCK DIAGRAM OF THE INPUT SECTION
BYPASS
PROCCLK = 28MHz
5MHz
CIC
FILTER
MIN. R = 4
CLKIN = 5MHz
HB/FIR FILTER
MAX. f_S = 4MHz
(EXCEEDED IN
BYPASS PATH)
500kHz = 85dB
BANDWIDTH
(NOT ACHIEVED
WITH CIC FILTER
PATH)
Without Interpolation, the CIC bypass path exceeds the HB/FIR filter
input sample rate and the CIC filter path will not yield the desired
85dB dynamic range band width of 500kHz.
FIGURE 4. STATEMENT OF THE PROBLEM
↑8 (0 STUFF) = 40MHz
4MHz
5MHz
CIC FILTER
R = ↓10
CLKIN = 40MHz
HB/FIR FILTER
500kHz = 85dB
BANDWIDTH
FIGURE 5. BLOCK DIAGRAM OF THE INTERPOLATION
APPROACH
10
FN4450.4
May 1, 2007