English
Language : 

ISL6742B_14 Datasheet, PDF (4/20 Pages) Intersil Corporation – Advanced Double-Ended PWM Controller
ISL6742B
Pin Descriptions (Continued)
PIN # SYMBOL
DESCRIPTION
14
VDD VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a 0.1µF or larger high frequency
ceramic capacitor as close to the VDD and GND pins as possible.
VDD is monitored for supply voltage undervoltage lock-out (UVLO). The start and stop thresholds track each other resulting in
relatively constant hysteresis.
15
VADJ A 0V to 5V control voltage applied to this input sets the relative delay or advance between OUTA/OUTB and OUTAN/OUTBN.
Voltages below 2.425V result in OUTAN/OUTBN being advanced relative to OUTA/OUTB. Voltages above 2.575V result in
OUTAN/OUTBN being delayed relative to OUTA/OUTB. A voltage of 2.50V ±75mV results in zero phase difference. A weak internal
50% divider from VREF results in no phase delay if this input is left floating.
The range of phase delay/advance is either zero or 40ns to 300ns with the phase differential increasing as the voltage deviation
from 2.5V increases. The relationship between the control voltage and phase differential is non-linear. The gain (Δt/ΔV) is low for
control voltages near 2.5V and rapidly increases as the voltage approaches the extremes of the control range. This behavior
provides the designer increased accuracy when selecting a shorter delay/advance duration.
When the PWM outputs are delayed relative to the SR outputs (VADJ < 2.425V), the delay time should not exceed 90% of the
deadtime as determined by RTD and CT.
16
SS Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The value of the capacitor
determines the rate of increase of the duty cycle during start-up. Although no minimum value of capacitance is required, it is
recommended that a value of at least 100pF be used for noise immunity.
SS may also be used to inhibit the outputs by grounding through a small transistor in an open collector/drain configuration.
4
FN8565.0
January 31, 2014