ISL6742B_14 Datasheet, PDF (15/20 Pages) Intersil Corporation – Advanced Double-Ended PWM Controller

ISL6742B
propagation delays between the PWM FETs and the SR FETs.
A voltage applied to VADJ controls the phase relationship.
Figures 12 and 13 demonstrate the delay relationships.
CT
OUTA
OUTB
OUTAN
(SR1)
OUTBN
(SR2)
FIGURE 12. WAVEFORM TIMING WITH PWM OUTPUTS DELAYED,
0V < VADJ < 2.425V
CT
OUTA
OUTB
OUTAN
(SR1)
OUTBN
(SR2)
FIGURE 13. WAVEFORM TIMING WITH SR OUTPUTS DELAYED,
2.575V < VADJ < 5.00V
Setting VADJ to VREF/2 results in no delay on any output. The no
delay voltage has a ±75mV tolerance window. Control voltages
below the VREF/2 zero delay threshold cause the PWM outputs,
OUTA/OUTB, to be delayed. Control voltages greater than the
VREF/2 zero delay threshold cause the SR outputs,
OUTAN/OUTBN, to be delayed. It should be noted that when the
PWM outputs, OUTA/OUTB, are delayed, the CS to output
propagation delay is increased by the amount of the added delay.
The delay feature is provided to compensate for mismatched
propagation delays between the PWM and SR outputs as may
be experienced when one set of signals crosses the primary-
secondary isolation boundary. If required, individual output
pulses may be stretched or compressed as required using
external resistors, capacitors, and diodes.
Slope Compensation
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles greater
than 50%. Slope compensation may be accomplished by
summing an external ramp with the current feedback signal or by
subtracting the external ramp from the voltage feedback error
signal. Adding the external ramp to the current feedback signal is
the more popular method.
From the small signal current-mode model [1] it can be shown
that the naturally-sampled modulator gain, F_m, without slope
compensation, is expressed in Equation 10:
F_m
=
------¹--------
S_nS_n
(EQ. 10)
where S_n is the slope of the sawtooth signal and t_SW is the
duration of the half-cycle. When an external ramp is added, the
modulator gain becomes Equation 11:
F_m
=
-----------------¹-------------------
(S_n + S_e)t_SW
=
------------¹--------------
m_cS_nt_SW
(EQ. 11)
where S_e is slope of the external ramp and:
m_c
=
1
+
-^S----^e-
S_n
(EQ. 12)
The criteria for determining the correct amount of external ramp
can be determined by appropriately setting the damping factor of
the double-pole located at half the oscillator frequency. The
double-pole will be critically damped if the Q-factor is set to 1,
over-damped for Q > 1, and under-damped for Q < 1. An
under-damped condition may result in current loop instability.
Q
=
------------------------¹-------------------------
π(m_c(1 – D) – 0.5)
(EQ. 13)
where D is the percent of on-time during a half cycle (half period
duty cycle). Setting Q = 1 and solving for S_e yields Equation 14:
S_e
=
S_n
⎛⎛
⎝⎝
1_π--
+
0.5_⎠⎞
------¹-------
1–D
–
1_⎠⎞
(EQ. 14)
Since S_n and S_e are the on-time slopes of the current ramp and
the external ramp, respectively, they can be multiplied by t_ON to
obtain the voltage change that occurs during t_ON.
V_e
=
V_n
⎛⎛
⎝⎝
1_--
π
+
0.5_⎠⎞
------¹-------
1–D
–
1_⎠⎞
(EQ. 15)
where V_n is the change in the current feedback signal during the
on time and V_e is the voltage that must be added by the external
ramp.
V_n can be solved for in terms of input voltage, current transducer
components, and output inductance yielding Equation 16:
V_e
=
-^t-^S----^W-------^â‹---^V----^O------^â‹---^R----^C----^S--
N_CT ⋅ L_O
⋅
N_-----S--
N_P
⎝⎛ ^1-_π^-
+
D
–
0.5_⎠⎞
V
(EQ. 16)
where R_CS is the current sense burden resistor, N_CT is the current
transformer turns ratio, L_O is the output inductance, V_O is the
output voltage, and N_S and N_P are the secondary and primary
turns, respectively.
15
FN8565.0
January 31, 2014